±15kV ESD-Protected, Quad,

Low-Voltage, SPST Analog Switches

10

______________________________________________________________________________________

GND

NC or

NO

-5V

V-

V+

IN

OFF

ON

OFF

Q = (

COM

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

+5V

IN

MAX4551

MAX4552

MAX4553

Figure 3. Charge Injection

tr < 20ns

tf < 20ns

50%

0V

LOGIC

INPUT

V-

-5V

300

Ω

NO

or NC

GND

(

)

SWITCH

INPUT

IN, EN

+3V

0V

COM

SWITCH

OUTPUT

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

35pF

+5V

V+

0V

MAX4551

MAX4552

MAX4553

50%

+3V

0V

0V

LOGIC

INPUT

SWITCH

OUTPUT 2

0V

LOGIC

INPUT

V-

-5V

GND

COM2

IN1, 2

COM1

V+

+5V

NO

NC

SWITCH

OUTPUT 1

MAX4553

Figure 1. Switching Time

Figure 2. Break-Before-Make Interval (MAX4553 only)

Test Circuits/Timing Diagrams