±15kV ESD-Protected, Quad,

Low-Voltage, SPST Analog Switches

_______________________________________________________________________________________

5

Note 2:

The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.

Note 3:

Guaranteed by design.

Note 4:

Note 5:

Resistance flatness is defined as the difference between the maximum and minimum on-resistance values, as measured

over the specified analog signal range.

Note 6:

Note 7:

Note 8:

Between any two switches.

Note 9:

Leakage testing for single-supply operation is guaranteed by testing with dual supplies.

ELECTRICAL CHARACTERISTICS—Single +3V Supply

+25°C

Charge Injection

COM_ to NO_, COM_ to NC_

On-Resistance

Q

C, E

500

Ω

IN_ Input Logic Threshold High

C, E

2.0

1.1

V

IN_ Input Logic Threshold Low

CONDITIONS

C, E

Figure 3

+25°C

200

400

15

pC

V

0V+

Analog Signal Range

(Note 3)

C, E

1.1

0.5

V

IN_ Input Current Logic High

or Low

C, E

-1

0.03

1

µA

+25°C

190

350

Turn-On Time

Figure 1

C, E

400

ns

+25°C

160

250

Turn-Off Time

Figure 1

C, E

300

ns

+25°C

10

50

Break-Before-Make Time Delay

(MAX4553 Only)

Figure 2

ns

+25°C

-1

0.05

1

V+ Supply Current

UNITS

MIN

TYP

MAX

(Note 2)

SYMBOL

PARAMETER

I+

C, E

-1

1

µA

SWITCH DYNAMIC CHARACTERISTICS (Note 4)

POWER SUPPLY

+25°C

±8

Contact Discharge IEC 1000-4-2

+25°C

±15

+25°C

±15

Human Body Model

On NC_ and NO_ Pins

per IEC 801-2

kV

Air Discharge IEC 1000-4-2

+25°C

±2.5

MIL-STD-883C Method 3015

All Pins

kV

LOGIC INPUT

SWITCH DYNAMIC CHARACTERISTICS

POWER SUPPLY

ESD PROTECTION

ANALOG SWITCH