Low-Voltage, CMOS Analog Multiplexers/Switches

with Enable Inputs and Address Latching

12

______________________________________________________________________________________

Figure 3. Break-Before-Make Interval

_________________________________Test Circuits/Timing Diagrams (continued)

V-

COM

V-

300

Ω

GND

ADDC

ADDB

ADDA

EN2

50

Ω

35pF

V+

V+

V+

MAX4530

NO0–NO7

+3V

EN1

V-

COM_

V-

300

Ω

GND

ADDA

ADDB

EN2

50

Ω

35pF

V+

V+

V+

MAX4531

NO0_–NO3_

+3V

EN1

V-

COM

V-

300

Ω

GND

ADD_

EN2

50

Ω

35pF

V+

V+

V+

MAX4532

V- = 0V FOR SINGLE-SUPPLY OPERATION.

REPEAT TEST FOR EACH SECTION.

NO_, NC_

+3V

EN1

tF < 20ns

tR < 20ns

0V

0V

90%

50%

V+

LE

LE

LE