1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

13

Rev D 2/17/15

8745B-21 DATA SHEET

Schematic Example

The schematic of the 8745B-21 layout example is shown in Figure

5A. The 8745B-21 recommended PCB board layout for this example

is shown in Figure 5B. This layout example is used as a general

guideline. The layout in the actual system will depend on the selected

component types, the density of the components, the density of the

traces, and the stack up of the P.C. board.

Figure 5A. 8745B-21 LVDS Zero Delay Buffer Schematic Example

SEL2

PLL_SEL

RD6

SP

RD4

SP

R4

100

VDD

RU3

1K

SP = Space (i.e. not intstalled)

SEL0

SEL3

RU4

1K

SEL[3:0] = 0101,

Divide by 2

R8

50

RD7

1K

(77.76 MHz)

VDDO

VDD

C1

0.1uF

Bypass capacitors located

near the power pins

RU5

SP

C16

10u

SEL3

VDDO

(U1-7)

Zo = 50 Ohm

VDDA

3.3V PECL Driver

SEL1

R9

50

VDD=3.3V

VDDO

R10

50

SEL0

Zo = 50 Ohm

RD5

1K

C11

0.01u

(U1-11)

C4

0.1uF

SEL2

(155.52 MHz)

LVDS_input

+

-

Zo = 100 Ohm Differential

R2

100

SEL1

RU7

SP

C2

0.1uF

R7

10

PLL_SEL

U1

ICS8745B-21

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

CLK

nCLK

MR

nFB_IN

FB_IN

SEL2

VDDO

nQFB

QFB

GND

VDDO

nQ

Q

GND

SEL3

VDDA

SEL1

SEL0

VDDI

PLL_SEL

RD3

SP

VDD

VDDO=3.3V

RU6

1K

3.3V