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DS_FT600Q-FT601Q IC Datasheet/FT601 USB 3.0 to FIFO Bridge

Version 1.01

Document No.: FT_001118 Clearance No.: FTDI#424

NOTE: There is no turnaround phase for BE pins as these remain inputs when the FIFO is being written to

by the master.

The waveform below shows a master write transaction where the FIFO at channel 1 uses all data space

first, the RXF_N deasserts when the FIFO data space is not available after D3. There are turn-a-round

cycles for DATA[15:8] after the command phase and at the end of the data transaction. The BE[3:0]

shows that the transaction is all in word aligned, all 4 bytes in D3 are valid at the last word strobe in this

transaction.

Figure 4.4 Multi-Channel FIFO mode master write transaction 2

The waveform below shows a master read of channel 1 followed by a master write to channel 1.

The channel number is selected in the command phase (DATA[7:0] = h’01 for channel 1 in this case),

and data is transferred on the same data pins multiplexed to a different channel.

Figure 4.5 Multi-Channel FIFO mode master read followed by write transaction

4.3 245 Synchronous FIFO mode Protocols

This slave bus uses one IN and one OUT FIFO channel while in this mode.

CLK is the clock output to the bus master, it can be configured as 66Mhz or 100Mhz.

TXE_N is an output signal, Transmit FIFO Empty. It is active low and when active it indicates the

Transmit FIFO has space and it is ready to receive data from the FIFO master.

RXF_N is an output signal, Receive FIFO Full. It is active low and when active it indicates the Receive

FIFO has data and it is ready to be read by the FIFO master.

OE_N is an input signal, Output Enable. It is active low and when it is driven low by the bus master, the

slave will drive the data and byte enable buses.

WR_N is an input signal, Write Enable. It is active low and when it is driven low by the bus master, the

master has write cycle access.

RD_N is an input signal, Read Enable. It is active low and when it is driven low by the bus master, the

master has read cycle access.

BE[3:0](BE[1:0] for FT600) is byte enable signal. In bus master read operation, the FT60X asserts the

signal for the valid bytes in a word strobe. In bus master write operation, the bus master assets the

signal for the valid bytes in a word strobe. Normally, all 4 bytes should be valid in a bus transaction

except in the last word strobe when the data transaction length not aligned at word boundary.