Serially Controlled, Low-Voltage,

8-Channel SPST Switch

14

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SCLK, each switch sequences one differential channel

at a time, starting with channel 7/0. After the first eight

bits have been sent, subsequent channel sequencing

can occur by repeating this sequence or, even faster,

by sending only one DIN high pulse and one CS low

pulse for each four clock pulses.

SPDT Switches

To use the MAX395 as a quad, single-pole/double-

throw (SPDT) switch, connect COM0 to NO1, COM2 to

NO3, COM4 to NO5, and COM6 to NO7, forming the

four “common” pins. Program these four switches with

pairs of instructions, as shown in Table 2.

Reset Function

RESET is the internal reset pin. It is usually connected

to a logic signal or V+. Drive RESET low to open all

switches and set the contents of the internal shift regis-

ter to zero simultaneously. When RESET is high, the

part functions normally and DOUT is sourced from V+.

RESET must not be driven beyond V+ or GND.

Power-Supply Considerations

Overview

The MAX395 construction is typical of most CMOS ana-

log switches. It has three supply pins: V+, V-, and

GND. V+ and V- are used to drive the internal CMOS

switches and to set the limits of the analog voltage on

any switch. Reverse ESD-protection diodes are inter-

nally connected between each analog signal pin and

both V+ and V-. If any analog signal exceeds V+ or V-,

one of these diodes will conduct. During normal opera-

tion, these (and other) reverse-biased ESD diodes leak,

forming the only current drawn from V+ or V-.

Virtually all the analog leakage current is through the

ESD diodes. Although the ESD diodes on a given sig-

nal pin are identical, and therefore fairly well balanced,

they are reverse biased differently. Each is biased by

either V+ or V- and the analog signal. This means their

leakages vary as the signal varies. The difference in the

two diode leakages to the V+ and V- pins constitutes

the analog signal-path leakage current. All analog leak-

FOUR CLOCK

PULSES

DIN

SCLK

D4

SW4

D0

SW0

Figure 7. Differential Multiplexer Input Control

CS

SCLK

DIN

MAX395

CS

SCLK

DIN

MAX395

CS

SCLK

DIN

MAX395

TO OTHER

SERIAL

DEVICES

DIN

SCLK

CS1

CS2

CS3

Figure 6. Addressable Serial Interface