8-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

2

REVISION B 07/17/15

9FGL08 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Connections

48 47 46 45 44 43 42 41 40 39 38 37

vSS_EN_tri 1

36 DIF5#

GNDXTAL 2

35 DIF5

XIN/CLKIN_25 3

34 vOE4#

X2 4

33 DIF4#

VDDXTAL3.3 5

32 DIF4

VDDREF3.3 6

31 VDDIO

vSADR/REF3.3 7

30 VDDA3.3

GNDREF 8

29 GNDA

GNDDIG 9

28 vOE3#

SCLK_3.3 10

27 DIF3#

SDATA_3.3 11

26 DIF3

VDDDIG3.3 12

25 vOE2#

13 14 15 16 17 18 19 20 21 22 23 24

vv prefix indicates internal 60KOhm pull down resistor

v

prefix indicates internal 120KOhm pull down resistor

^

prefix indicates internal 120KOhm pull up resistor

48-pin VFQFPN, 6x6 mm, 0.4mm pitch

9FGL0841/51/P1

epad is GND

SADR

Address

0

1101000

1

1101010

State of SADR on first application

of CKPWRGD_PD#

+

Read/Write Bit

x

x

True O/P

Comp. O/P

0X

X

1

1

0

Running

Running

Running

11

1

Running

10

X

1. The output state is set by B11[1:0] (Low/Low default)

3. Input polarities defined at default values for 9FGL0841/0851.

4. See SMBus description for Byte 3, bit 4

REF

CKPWRGD_PD#

SMBus

OE bit

2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when

CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is

running..

DIFx/DIFx#

OEx# Pin

Pin Number

VDD

VDDIO

GND

52

XTAL OSC

68

REF Power

12

9

Digital (dirty)

Power

20,38

13,21,31,39,

47

22,29,40,

49

DIF outputs

30

29

PLL Analog

Description