REVISION B 07/17/15

11

6-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

9FGL06 DATASHEET

Byte 0

Name

Control Function

Type

0

1

Default

Bit 7

DIF OE5

Output Enable

RW

Enabled

1

Bit 6

DIF OE4

Output Enable

RW

Enabled

1

Bit 5

X

Bit 4

DIF OE3

Output Enable

RW

Enabled

1

Bit 3

DIF OE2

Output Enable

RW

Enabled

1

Bit 2

DIF OE1

Output Enable

RW

Enabled

1

Bit 1

X

Bit 0

DIF OE0

Output Enable

RW

See B11[1:0]

Enabled

1

SMBus Table: SS Readback and Control Register

Byte 1

Name

Control Function

Type

0

1

Default

Bit 7

SSENRB1

SS Enable Readback Bit1

R

Latch

Bit 6

SSENRB1

SS Enable Readback Bit0

R

Latch

Bit 5

SSEN_SWCNTRL

Enable SW control of SS

RW

SS control locked

Values in B1[4:3]

control SS amount.

0

Bit 4

SSENSW1

SS Enable Software Ctl Bit1

0

Bit 3

SSENSW0

SS Enable Software Ctl Bit0

0

Bit 2

X

Bit 1

AMPLITUDE 1

RW

00 = 0.55V

01= 0.65V

1

Bit 0

AMPLITUDE 0

RW

10 = 0.7V

11 = 0.8V

0

1. B1[5] must be set to a 1 for these bits to have any effect on the part.

SMBus Table: DIF Slew Rate Control Register

Byte 2

Name

Control Function

Type

0

1

Default

Bit 7

DIF OE5

Output Enable

RW

Enabled

1

Bit 6

DIF OE4

Output Enable

RW

Enabled

1

Bit 5

X

Bit 4

DIF OE3

Output Enable

RW

Enabled

1

Bit 3

DIF OE2

Output Enable

RW

Enabled

1

Bit 2

DIF OE1

Output Enable

RW

Enabled

1

Bit 1

X

Bit 0

DIF OE0

Output Enable

RW

See B11[1:0]

Enabled

1

Note: See "Low-Power HCSL Outputs" table for slew rates.

SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register

Byte 3

Name

Control Function

Type

0

1

Default

Bit 7

RW

00 = Slowest

01 =Slow

0

Bit 6

RW

10 = Fast

11 = Fastest

1

Bit 5

REF Power Down Function

Wake-on-Lan Enable for REF

RW

REF disabled in

Power Down

REF runs in Power

Down

0

Bit 4

REF OE

REF Output Enable

RW

Enabled

1

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

1. The disabled state depends on Byte11[1:0]. '00' = Low, '01'=HiZ, '10'=Low, '11'=HIgh

Byte 4 is Reserved

See B11[1:0]

Reserved

See B11[1:0]

Reserved

See B11[1:0]

Reserved

See B11[1:0]

Reserved

Reserved

Reserved

Reserved

Reserved

1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)

00' for SS_EN_tri = 0, '01' for SS_EN_tri

= 'M', '11 for SS_EN_tri = '1'

00' = SS Off, '01' = -0.25% SS,

'10' = Reserved, '11'= -0.5% SS

Reserved

Controls Output Amplitude

REF

Slew Rate Control