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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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9DB433 датащи(PDF) 7 Page - Integrated Circuit Systems |
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9DB433 датащи(HTML) 7 Page - Integrated Circuit Systems |
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7 / 17 page  9DB433 FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 7 9DB433 REV G 08/25/15 Electrical Characteristics–PCIe Phase Jitter Parameters Clock Periods–Differential Outputs Tracking Spread Spectrum Clock Periods–Differential Outputs not Tracking Spread Spectrum TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes tjphPCIeG1 PCIe Gen 1 30 86 ps (p-p) 1,2,3 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 1.0 3 ps (rms) 1,2 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 2.2 3.1 ps (rms) 1,2 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.5 1 ps (rms) 1,2,4 tjphPCIeG1 PCIe Gen 1 1 5 ps (p-p) 1,2,3 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.1 0.1 ps (rms) 1,2 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 0.2 0.3 ps (rms) 1,2 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.0 0.1 ps (rms) 1,2,4 1 Applies to all outputs. 4 Subject to final radification by PCI SIG. tjphPCIeG2 2 See http://www.pcisig.com for complete specs tjphPCIeG2 Phase Jitter, PLL Mode Additive Phase Jitter, Bypass Mode 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+ Absolute Period Short-term Average Long-Term Average Period Long-Term Average Short-term Average Period Minimum Absolute Period Minimum Absolute Period Minimum Absolute Period Nominal Maximum Maximum Maximum 9.949 9.999 10.024 10.025 10.026 10.051 10.101 ns 1,2,3 Symbol DIF 100 Notes Definition Units Measurement Window 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+ Absolute Period Short-term Average Long-Term Average Period Long-Term Average Short-term Average Period Minimum Absolute Period Minimum Absolute Period Minimum Absolute Period Nominal Maximum Maximum Maximum DIF 100M 9.949 9.999 10.000 10.001 10.051 ns 1,2,3 1Guaranteed by design and characterization, not 100% tested in production. 3 Driven by PCIe output of main clock, PLL Mode or Bypass mode 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+ accuracy requirements. The buffer itself does not contribute to ppm error. Notes Measurement Window Units Symbol Definition |
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