The MAX3100 X1 input can be driven directly by an

external CMOS clock source. The trip level is approxi-

made to X2 in this mode. If a TTL or non-CMOS clock

source is used, AC couple with a 10nF capacitor to X1.

The peak-to-peak swing on the input should be at least

2V for reliable operation.

9-Bit Networks

The MAX3100 supports a common multidrop communi-

cation technique referred to as 9-bit mode. In this mode,

the parity bit is set to indicate a message that contains a

header with a destination address. The MAX3100 parity

mask can be set to generate interrupts for this condition.

Operating a network in this mode reduces the process-

ing overhead of all nodes by enabling the slave con-

trollers to ignore most message traffic. This can relieve

the remote processor to handle more useful tasks.

In 9-bit mode, the MAX3100 is set up with 8 bits plus

parity. The parity bit in all normal messages is clear, but

is set in an address-type message. The MAX3100 pari-

ty-interrupt mask is enabled to generate an interrupt on

high parity. When the master sends an address mes-

sage with the parity bit set, all MAX3100 nodes issue an

interrupt. All nodes then retrieve the received byte to

compare to their assigned address. Once addressed,

the node continues to process each received byte. If the

node was not addressed, it ignores all message traffic

until a new address is sent out by the master.

The parity/9th-bit interrupt is controlled only by the data

in the receive register, and is not affected by data in

the FIFO, so the most effective use of the parity/9th-bit

interrupt is with FIFO disabled. With the FIFO disabled,

received nonaddress words can be ignored and not

even read from the UART.

SIR IrDA Mode

The MAX3100’s IrDA mode can be used to communicate

with other IrDA SIR-compatible devices, or to reduce

power consumption in opto-isolated applications.

In IrDA mode, a bit period is shortened to 3/16 of a

baud period (1.6µs at 115,200 baud) (Figure 9). A data

zero is transmitted as a pulse of light (TX pin = logic

low, RX pin = logic high).

In receive mode, the RX signal’s sampling is done

halfway into the transmission of a high level. The sam-

pling is done once, instead of three times, as in normal

mode. The MAX3100 ignores pulses shorter than

approximately 1/16 of the baud period. The IrDA device

that is communicating with the MAX3100 must be set to

transmit pulses at 3/16 of the baud period. For compati-

bility with other IrDA devices, set the format to 8-bit

data, one stop, no parity.

IrDA Module

The MAX3100 was optimized for direct optocoupler

drive, whereas IrDA modules contain inverting buffers.

Invert the RX and TX outputs as shown in Figure 10.

8051 Example: IrDA to RS-232 Converter

Figure 10 shows the MAX3100 with an 8051 µC. This

circuit receives IrDA data and outputs standard RS-232

data. Although the 8051 contains an internal UART, it

does not support IrDA or high-speed communications.

The MAX3100 can easily interface to the 8051 to sup-

port these high-performance communications modes.

The 8051 does not have an SPI interface, so communi-

cation with the MAX3100 is accomplished with port

pins and a short software routine (Figure 12a).

The software routine polls the IRQ output to see if data

is available from the MAX3100 UART. It then shifts the

data out, using the 8051 port pins, and transmits it out

the RS-232 side through the MAX3221 driver. The 8051

simultaneously monitors its internal UART for incoming

communications from the RS-232 side, and transmits

this data out the IrDA side through the MAX3100. The

low-level routine (UTLK) is the core routine that sends

and receives data over the port pins to simulate an SPI

port on the 8051. This technique is useful for any 8051-

based MAX3100 port-pin-interfaced application.

SPI/Microwire-Compatible

UART in QSOP-16

______________________________________________________________________________________

15

NORMAL

RX

UART FRAME

DATA BITS

0

1

1

1

1

1

0

0

0

0

NORMAL UART

TX

1

1

1

1

1

0

0

0

0

IrDA

RX

IrDA

TX

Figure 9. IrDA Timing