IR3552 datasheet(13/23 Pages) IRF

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IR3552

40A Integrated PowIRstage

February 19, 2014 | FINAL

GENERAL DESCRIPTION

The IR3552 contains a high-efficiency and high

speed MOSFET driver optimized to drive a pair of

integrated

control

and

synchronous

N-channel

MOSFETs up to 1.5MHz. The patented IR Active Tri-

Level (ATL) feature allows complete enable and

disable control of both MOSFET pairs through the

PWM input signal from the controller. The timing and

voltage levels of ATL are shown in Figure 6.

During

normal

operation

the

PWM

transitions

between low and high voltage levels to drive the

synchronous and control MOSFETs. The PWM

signal falling edge transition to a low voltage

threshold initiates the high-side driver turn off after a

short propagation delay. The dead time control

circuit monitors the internal high gate signals and

respective SW voltages to ensure the control

MOSFET is turned off before turning on the

synchronous MOSFET.

The PWM rising edge transition through the high-

side turn on threshold initiates the turn off of the

synchronour MOSFET after a small propagation

delay. The adaptive dead time circuit provides the

appropriate

dead

time

determining

the

synchronous MOSFET gate voltage has crossed the

lower threshold before allowing the High Gate

voltage to rise and turn on the control MOSFET.

THEORY OF OPERATION

POWER-ON RESET (POR)

The

IR3552

incorporates

power-on

reset

protection. This ensures that both the high- and low-

side output drivers are active only after the device

supply voltage VCC and VDRV both have exceeded

a certain minimum operating threshold. The VCC

and VDRV supplies are monitored and both the

drivers are set to the low state, holding both external

MOSFETs off. Once both VCC and VDRV cross the

rising POR threshold and if the IR3552 is in IR ATL

mode, the outputs are held in the low state until a

transition

from

tri-state

active

operation

detected at the PWM input. For standar Tri-state

PWM mode, the POR operation is the same except

the driver does not look for an input tri-state before

functioning. During normal operation the drivers

continue to remain active until VCC or VDRV fall

below their respective falling POR thresholds.

INTEGRATED BOOTSTRAP PFET

The IR3552 features an integrated bootstrap PFET

to reduce external component count. This enables

the IR3552 to be used effectively in cost and space

sensitive designs.

The bootstrap circuit is used to establish the high

side MOSFET gate driver bias voltage and consists

of a PFET (which includes a body diode in parallel)

and an external capacitor connected between the

SW and BOOST pins. The external bootstrap

capacitor is charged through the PFET when the SW

node is low.

STANDARD PWM TRISTATE MODE

If the MODE pin is grounded, the IR3552 accepts

regular three-level 3.3V PWM input signals. As

shown in Figure 5, when PWM input is above

VPWM_HIGH, the synchronous MOSFET is turned off

and the control MOSFET is turned on. When PWM

input is below VPWM_LOW, the control MOSFET is

turned off and synchronous MOSFET is turned on. If

PWM pin is floated, the built-in resistors pull the

PWM pin into a tri-state region centered around

1.6V.

IR ACTIVE TRI-LEVEL (ATL) PWM INPUT

SIGNAL

When the MODE pin is tied to VCC, the IR3552 gate

drivers are driven by a patented tri-level PWM

control signal provided by the IR digital PWM

controllers, as shown in Figure 4. During normal

operation, the rising and falling edges of the PWM

signal transition between 0V and 1.8V to control

pulse width modulation of the integrated MOSFETs.

To force both MOSFETs off simultaneously, the

PWM signal crosses a tri-state voltage level higher

than the tri-state high threshold. This threshold

based tri-state results in a very fast disable for both

the MOSFET pairs with only a small tri-state

propagation delay. MOSFET switching resumes

when the PWM signal falls below the tri-state

threshold into the normal operating voltage range.

This fast tri-state operation eliminates the need for

any tri-state hold-off time of the PWM signal to dwell

in the shutdown window. Dedicated disable or

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