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LD1024 датащи(PDF) 21 Page - LDT Co., Ltd |
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LD1024 датащи(HTML) 21 Page - LDT Co., Ltd |
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21 / 22 page ![]() Ver2.1 21 LD1024 16-Channel, Constant-Current LED Driver with LED Open Detection LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Tel. +82 41 520 7300 Fax. +82 41 520 7337 www.ldt.co.kr STATUS INFORMATION DATA (SID) The latched LED open detection (LOD) error and pre-thermal warning (PTW) in the SID data latch are shifted out onto the DOUT pin with each rising edge of CLK. If a PTW is reported, all LOD error bits are set to '1'. The SID data are written over the data in the on/off control shift register at the rising edge of LAT. Therefore, the previous data in the on/off control shift register are lost when SID information is latched in. Figure 20 shows the SID bit assignments. See Figure 7 for the read timing of SID. When the IC is powered on, the initial LOD data are invalid. Therefore, LOD data must be read after the rising edge of OEB. Table 3 shows a truth table for LOD and PTW CONDITION SID DATA LED open detection (LODn) LED is connected (VOUTn > VLOD) '0' (low level at DOUT) (VOUTn ≤ VLOD and output on) '1' (high level at DOUT); set to the bit that has an LED error condition Pre-thermal Warning(PTW) IC temperature is low (IC temperature ≤ T(PTW) ) Depend LED open error IC temperature is high (IC temperature > T(PTW)) All bits = '1' (high level at DOUT) Table 2. LOD and PTW Truth Table Figure 15. Status Information Data Configuration OUT15 LOD Data (LOD 15) 15 OUT15 LOD Data (LOD 14) 14 OUT15 LOD Data (LOD 13) 13 OUT15 LOD Data (LOD 12) 12 OUT15 LOD Data (LOD 3) OUT15 LOD Data (LOD 2) OUT15 LOD Data (LOD 1) OUT15 LOD Data (LOD 0) 3 2 1 0 LSB MSB 11 4 On/Off Data for OUT15 15 On/Off Data for OUT14 14 On/Off Data for OUT13 13 On/Off Data for OUT12 12 On/Off Data for OUT3 On/Off Data for OUT2 On/Off Data for OUT1 On/Off Data for OUT0 3 2 1 0 LSB MSB 11 4 DIN CLK SID Data Latch (1 Bit x 16 Channels) SID Control Shift Register (1 Bit x 16 Channels) All Bits Become ‘1’ When the IC is in a PTW (Pre-Thermal Warning) Condition DOUT The 16 bits in the SID latch are loaded into the on/off shift register at the rising edge of LAT. |
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