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+3V, 8-Bit ADC with 1µA Power-Down

4

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PARAMETER

SYMBOL

CONDITIONS

MAX152C/E

MIN

MAX

MAX152M

MIN

MAX

UNITS

WR Pulse Width

0.6

10

0.66

10

0.8

10

µs

Delay Time Between

WR and RD Pulses

0.8

0.9

1.0

µs

RD Pulse Width

400

500

600

ns

400

500

600

ns

RD to INT Delay

300

340

400

ns

1.8

2.06

2.4

µs

Conversion Time

(RD Mode)

2.0

2.3

2.6

µs

Power-Up Time

0.9

1.2

1.4

µs

CS to RD,WR

Setup Time

0

0

0

ns

CS to RD,WR

Hold Time

0

0

0

ns

CS to RDY

Delay

100

120

140

ns

WR to INT Delay

0.7

1.45

1.6

1.8

RD Pulse Width

WR-RD mode,

(Figure 5)

180

220

250

ns

Data Access Time

(Note 7)

180

220

250

ns

WR to INT Delay

180

200

240

ns

Data Access Time

After

INT (Note 7)

Stand-alone mode,

100

130

150

ns

Data Access Time

(RD Mode) (Note 7)

+100

+150

ns

RD to INT Delay

(RD Mode)

100

160

170

180

ns

Data Hold Time

(Note 8)

100

130

150

ns

450

600

700

ns

ALL GRADES

MIN

TYP

MAX

Conversion Time

(WR-RD Mode)

Delay Time Between

Conversions

Data Access Time

(Note 7)

WR-RD mode,

(Figure 6)

WR-RD mode,

(Figure 6)

WR-RD mode,

(Figure 5)

+130

µs

TIMING CHARACTERISTICS

Note 6: Input control signals are specified with tr = tf = 5ns, 10% to 90% of +3.0V, and timed from a voltage level of 1.3V. Timing

delays get shorter at higher supply voltages. See the Converson Time vs. Supply Voltage graph in the

Typical Operating

Characteristics to extrapolate timing delays at other power-supply voltages.

Note 7: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V.

Note 8: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.

Stand-alone mode,