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MAX1270ACAI датащи(PDF) 16 Page - Maxim Integrated Products |
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MAX1270ACAI датащи(HTML) 16 Page - Maxim Integrated Products |
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16 / 20 page ![]() Multirange, +5V, 8-Channel, Serial 12-Bit ADCs 16 ______________________________________________________________________________________ Power-Down Mode To save power, configure the converter into low-current shutdown mode between conversions. Two program- mable power-down modes are available in addition to a hardware shutdown. Select STBYPD or FULLPD by pro- gramming PD0 and PD1 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. For example, if the control byte contains PD1 = 0, then the chip remains powered up. If PD1 = 1, then the chip powers down at the end of conversion. In all power- down modes, the interface remains active and conver- sion results can be read. Input overvoltage protection is active in all power-down modes. The first logical 1 on DIN after CS falls is interpreted as a start condition, and powers up the MAX1270/ MAX1271 from a software selected STBYPD or FULLPD condition. For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7µF capacitor at REF. This is a DC state that does not degrade after power-down of any duration. In FULLPD mode, only the bandgap reference is active. Connect a 33µF capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for ref- erence recovery prior to conversion. This allows con- version to begin immediately after power-up. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50µs for settling time. Auto-Shutdown Selecting STBYPD on every conversion automatically shuts down the MAX1270/MAX1271 after each conversion without requiring any start-up time on the next conversion. REF 10k Ω 2.5V 2.5V REFADJ AV = 1.638 MAX1270 MAX1271 4.7 µF CREF 0.01 µF Figure 13c. External Reference—Reference at REFADJ REF VDD 10k Ω 2.5V 4.096V REFADJ AV = 1.638 MAX1270 MAX1271 4.7 µF CREF Figure 13b. External Reference—Reference at REF REF 10k Ω 2.5V REFADJ 0.01 µF AV = 1.638 MAX1270 MAX1271 4.7 µF CREF Figure 13a. Internal Reference |
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