400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

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13

ground point) at GND, separate from the logic ground.

Connect all other analog grounds and GND to this star

ground point for further noise reduction. No other digital

system ground should be connected to this single-point

analog ground. The ground return to the power supply for

this ground should be low impedance and as short as

possible for noise-free operation.

the ADC’s high-speed comparator. Bypass this supply to

the single-point analog ground with 0.1µF and 10µF

bypass capacitors. Minimize capacitor lead lengths for

best supply-noise rejection. To reduce the effect of sup-

ply noise, a 10

Ω resistor can be connected as a lowpass

filter to attenuate supply noise (Figure 14).

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the endpoints of the transfer function,

once offset and gain errors have been nullified. The

static linearity parameters for the MAX1084/MAX1085

are measured using the endpoints method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of 1LSB or less guarantees no

missing codes and a monotonic transfer function.

Aperture Jitter

the time between the samples.

Aperture Delay

falling edge of CS and the instant when an actual sam-

ple is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The theoretical minimum analog-

to-digital noise is caused by quantization error and

results directly from the ADC’s resolution, (N bits):

CS

SCLK

DOUT

9

8

1

S0

D9

D8

D7

D6

D4

D3

D2

D1

D0

S1

D5

FIRST BYTE READ

SECOND BYTE READ

HIGH-Z

HIGH-Z

CS

SCLK

DOUT

14

12

1

D9

D8

D7

D6

D2

D3

D4

D1

D0

S1

S0

HIGH-Z

HIGH-Z

D5

Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)

Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)