Preliminary Datasheet

LP6342

LP6342-03

Version 1.3 Datasheet

Oct.-2011

www.lowpowersemi.com

12 / 15

For the condition where the step-down converter is in

dropout at 100% duty cycle, the total device dissipation

reduces to:

Since RDS(ON), quiescent current, and switching losses all

vary with input voltage, the total losses should be

investigated over the complete input voltage range. Given

the total losses, the maximum junction temperature can be

derived from the θJA for the DFN-10 package which is

45°C/W.

Vout=(R1/R2+1)*VFB

VIN

2.2uH

R2

R1

EN

1

SW

7

FB

5

Vin

2

Vin

3

SW

8

LP6342

Vout_2A

22pF

C1

10uF

C2

22uF

Layout Guidance

When laying out the PC board, the following layout

guideline should be followed to ensure proper operation of

the LP6342:

1. The exposed pad (EP) must be reliably soldered to the

GND plane. A PGND pad below EP is strongly

recommended.

2. The power traces, including the GND trace, the SW trace

and the IN trace should be kept short, direct and wide to

allow large current flow. The L1 connection to the SW pins

should be as short as possible. Use several VIA pads when

routing between layers.

3. The input capacitor (C1) should connect as closely as

possible to IN (Pin 2) and AGND (Pins 6) to get good

power filtering.

4. Keep the switching node, SW (Pins 7 and 8) away from

the sensitive FB/OUT node.

5. The feedback trace or OUT pinshould be separate from

any power trace and connect as closely as possible to the

load point. Sensing along a high-current load trace will

degrade DC load regulation. If external feedback resistors

are used, they should be placed as closely as possible to the

FB pin (Pin 5) to minimize the length of the high

impedance feedback trace.

6. The output capacitor C2 and L1 should be connected as

closely as possible. The connection of L1 to the SW pin

should be as short as possible and there should not be any

signal lines under the inductor.

7. The resistance of the trace from the load return to

PGND should be kept to a minimum. This will help to

minimize any error in DC regulation due to differences in

the potential of the internal signal ground and the power

ground.