RT9715CGF datasheet(11/12 Pages) RICHTEK

11 / 12 page

RT9715CA

DS9715CA-00 April 2015

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Layout Consideration

In order to meet the voltage drop, droop, and EMI

requirements, careful PCB layout is necessary. The

following guidelines must be followed :



Locate the ceramic bypass capacitors as close as

possible to the VIN pins of the RT9715CA.



Place a ground plane under all circuitry to lower both

resistance and inductance and improve DC and transient

performance (Use a separate ground and power plans if

possible).



Keep all VBUS traces as short as possible and use at

least 50-mil, 2 ounce copper for all VBUS traces.



Avoid vias as much as possible. If vias are necessary,

make them as large as feasible.



Place cuts in the ground plane between ports to help

reduce the coupling of transients between ports.



Locate the output capacitor and ferrite beads as close

to the USB connectors as possible to lower impedance

(mainly inductance) between the port and the capacitor

and improve transient load performance.



Locate the RT9715CA as close as possible to the output

port to limit switching noise.

Figure 2. Derating Curve of Maximum Power Dissipation

GND

GND_BUS

VIN

VOUT

VBUS

VIN

FLG

The input capacitor should

be placed as close as

possible to the IC.

Figure 3

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

Where TJ(MAX) is the maximum operation junction

temperature 100

°C, TAis the ambient temperature and the

θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT9715CA, where TJ(MAX) is the maximum junction

temperature of the die (100

°C) and TA is the maximum

ambient temperature. The junction to ambient thermal

resistance

θJA is layout dependent. For SOT-23-5 package,

the thermal resistance

θJA is 250°C/W on the standard

JEDEC 51-3 single-layer thermal test board. The maximum

power dissipation at TA = 25

°C can be calculated by

following formula :

PD(MAX) = (100

°C − 25°C) / (250°C/W) = 0.3W for

SOT-23-5 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 2 of derating

curves allows the designer to see the effect of rising

ambient temperature on the maximum power allowed.

0.0

0.1

0.2

0.3

0.4

0.5

2030

405060

7080

90 100

Ambient Temperature (°C)

Single Layer PCB

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