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RFSA2644

DS120706

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.

Serial Port Interface

Truth Table

SPI Timing Diagram

Programming Example - 6-Bit

Control Bit

Relative Gain

Setting

C16

C8C4

C2C1

C0.5

11

111

1

Max gain

11

111

0

-0.5dB

11

110

1

-1dB

11

101

1

-2dB

11

011

1

-4dB

10

111

1

-8dB

01

111

1

-16dB

00

000

0

-31.5dB

SPI Timing Diagram Specifications

Parameter

Limit

Unit

Comment

Logic Voltage Levels

t1

25

MHz max

CLK Frequency

State

Logic

t2

20

ns min

CLK High

Low

0V to 0.8V

t3

20

ns min

CLK Low

High

2.0V to 5.0V

t4

5

ns min

DATA to CLK Setup Time

t5

5

ns min

DATA to CLK Hold Time

Power-up Programming Truth Table

t6

30

ns min

Data Valid

PUP

Attenuator Setting

t7

5

ns min

LE to CLK Setup Time

Low

Attenuation at max, 31.5dB

t8

5

ns min

CLK to LE Setup Time

High

Attenuation at min, 0dB

t9

10

ns min

LE Pulse Width

t10

20

ns max

Output Set

RFS

CLK

DATA

LE

DOUT

SPI Ti

264

t6

t

t2

t4

t7

ing Diagra

1

t3

t5

t8

t9

t10