FORWARD

REVERSE

2

4

1

4

2

2

4

1

4

2

2

4

1

4

2

2

4

1

4

2

A

B

UPCLK

(7183LV)

DNCLK

(7183LV)

CLK

(7184LV)

UP/DN

(7184LV)

DIRECTION

PULSE

CURRENT

MIRROR

FILTER

FILTER

A

B

MODE

MUX

AND

BUFFER

8

7

UPCK or CLK

DNCK or UP/DN

1

4

5

6

2

3

FIGURE 3. LS7183, LS7184 BLOCK DIAGRAM

RBIAS

INHIBIT

LOGIC

MODE

DECODE

1M

1M

7183/84-071201-3

NOTE: Output clocks labelled 1, 2 and 4 have the following interpretations.

1: Generated in x1, x2 and x4 modes

2: Generated in x2 and x4 modes only

4: Generated in x4 mode only

FIGURE 2. LS7183, LS7184 INPUT/OUTPUT TIMING

The information included herein is believed to be

accurate and reliable. However, LSI Computer Systems,

Inc. assumes no responsibilities for inaccuracies, nor for

any infringements of patent rights of others which may

result from its use.