UPD98405 datasheet(13/64 Pages) NEC

13 / 64 page

Data Sheet S12689EJ2V0DS00

µµµµPD98405

(2/3)

Pin Name

Pin No.

I/O

I/O Level

Function

SIZE2

SIZE1

SIZE0

TTL

Burst size.

These pins indicate the size of current DMA transfer. They are

used to interface with a bus (such as S bus) that requires an

explicit burst size.

SIZE2

SIZE1

SIZE0

Function

1-word transfer

2-word burst

4-word burst

8-word burst

16-word burst

12-word burst

Others

Undefined

DR/W_B

TTL

DMA read/write.

This pin indicates the direction of DMA access.

1: Read access

0: Write access

ATTN_B

294

TTL

Attention (DMA request).

The

µPD98405 makes the ATTN_B signal low when it is to

execute a DMA operation. The ATTN_B signal becomes

inactive in synchronization with the rising edge of CLK when

only one more word of data is to be transferred by means of

DMA.

GNT_B

291

TTL

Bus enable.

The GNT_B signal goes low when the bus arbiter grants the

µPD98405 the bus mastership in response to a DMA request

from the

µPD98405. When the µPD98405 detects that the

GNT_B signal has gone low, it starts a DMA operation,

assuming that the bus mastership has been granted.

RDY_B

TTL

Target device ready.

This signal informs the

µPD98405 in the DMA cycle that the

target device is ready for input/output. The

µPD98405 makes

the RDY_B signal low if valid data exists on AD31 through AD0

when it executes a DMA read operation. When executing a

DMA write operation, the

µPD98405 makes the ATTN_B signal

low if the target device is ready for reception.

The timing at which the

µPD98405 samples the RDY_B and

ABRT_B signals can be bring forward by 1 clock depending on

the setting of an internal register (GMR register).

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