LTC2428CG datasheet(22/28 Pages) LINER

22 / 28 page

LTC2424/LTC2428

APPLICATIONS INFORMATION

full-scale shift, see Figure 19. To simplify the analysis of

input dynamic current, two separate cases are assumed:

large capacitance at VIN (CIN > 0.01µF) and small capaci-

tance at VIN (CIN < 0.01µF).

If the total capacitance at VIN (see Figure 20) is small

(< 0.01

µF), relatively large external source resistances (up

to 20k for 20pF parasitic capacitance) can be tolerated

without any offset/full-scale error.

ANTIALIASING

One of the advantages delta-sigma ADCs offer over con-

ventional ADCs is on-chip digital filtering. Combined with

a large oversampling ratio, the LTC2424/LTC2428 signifi-

cantly simplify antialiasing filter requirements.

The digital filter provides very high rejection except at

integer multiples of the modulator sampling frequency

(fS), see Figure 21. The modulator sampling frequency is

256 • FO, where FO is the notch frequency (typically 50Hz

or 60Hz). The bandwidth of signals not rejected by the

digital filter is narrow (

≈0.2%)comparedtothebandwidth

of the frequencies rejected.

Figure 18. LTC2424/LTC2428 Equivalent Analog Input Circuit

FSSET

CHX

ADCVCC

(PIN 2)

RSW

AVERAGE INPUT CURRENT:

IDC = 0.25(VIN – 0.5 • VREF) • f • CEQ

IREF

ADCVCC

(PIN 2)

IIN(LEAK)

±IDC

MUXVCC

(PIN 8)

IIN(MUX)

RSW

Ω

CEQ

1pF (TYP)

RSW

SELECTED

CHANNEL

24248 F18

fOUT = 50Hz, INTERNAL OSCILLATOR: f = 128kHz

fOUT = 60Hz, INTERNAL OSCILLATOR: f = 153.6kHz

EXTERNAL OSCILLATOR: 2.56kHz

≤ f ≤ 307.2kHz

ZSSET

ADCIN

MUXOUT

Figure 19. Offset/Full-Scale Shift

Figure 20. An RC Network at CH0 to CH7

TUE

VREF/2

VIN

24248 F19

VREF

CIN

24248 F20

INTPUT

SIGNAL

SOURCE

RSOURCE

CH0 TO

CH7

LTC2424/

LTC2428

CPAR

≅20pF

Figure 21. Sync4 Filter Rejection

INPUT FREQUENCY

–60

–40

24248 F21

–80

–100

fS/2

–120

–140

–20

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