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LTC1736

APPLICATIO S I FOR ATIO

Table 1. VID Output Voltage Programming

VID4

VID3

VID2

VID1

VID0

VOUT (V)

0000

2.000V

0001

1.950V

0010

1.900V

0011

1.850V

0100

1.800V

0101

1.750V

0110

1.700V

0111

1.650V

1000

1.600V

1001

1.550V

1010

1.500V

1011

1.450V

1100

1.400V

1101

1.350V

1110

1.300V

1111

0000

1.275V

0001

1.250V

0010

1.225V

0011

1.200V

0100

1.175V

0101

1.150V

0110

1.125V

0111

1.100V

1000

1.075V

1001

1.050V

1010

1.025V

1011

1.000V

1100

0.975V

1101

0.950V

1110

0.925V

1111

Note: *, ** represents codes without a defined output voltage as specified in

Intel specifications. The LTC1736 interprets these codes as valid inputs and

produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.

Topside MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connectedtotheBOOST

pin supplies the gate drive voltage for the topside MOSFET.

Capacitor CB in the Functional Diagram is charged though

external diode DB from INTVCC when the SW pin is low.

Note that the voltage across CB is about a diode drop below

INTVCC. When the topside MOSFET is to be turned on, the

driver places the CB voltage across the gate-source of the

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage SW rises to VIN

and the BOOST pin rises to VIN + INTVCC. The value of the

boost capacitor CB needs to be 100 times greater than the

total input capacitance of the topside MOSFET. In most

applications 0.1

µF to 0.33µF is adequate. The reverse

breakdown on DB must be greater than VIN(MAX) .

When adjusting the gate drive level, the final arbiter is the

total input current for the regulator. If you make a change

and the input current decreases, then you improve the

efficiency. If there is no change in input current, then there

is no change in efficiency.

SENSE +/SENSE – Pins

The common mode input range of the current comparator

is from 0V to 1.1(INTVCC). Continuous linear operation is

guaranteed throughout this range allowing output volt-

ages anywhere from 0.8V to 7V (although the VID control

pins only program a 0.925V to 2.00V output range). A

differential NPN input stage is used and is biased with

internal resistors from an internal 2.4V source as shown

in the Functional Diagram. This causes current to flow out

of both sense pins to the main output. This forces a

minimum load current which is sunk by the internal

resistive divider resistors R1 and R2. The maximum

current flowing out of the sense pins is:

ISENSE+ + ISENSE– = (2.4V – VOUT)/24k

Remember to take this current into account if resistance is

placed in series with the sense pins for filtering.

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