7

LTC1658

OPERATIO

Serial Interface

on the rising edge of the clock. The MSB is loaded first. The

DAC register loads the data from the shift register when

CS/LD is pulled high. The clock is disabled internally when

CS/LD is high. Note: CLK must be low before CS/LD is

pulled low to avoid an extra internal clock pulse. The input

word must be 16 bits wide. The last two bits are don’t

cares.

The buffered output of the 16-bit shift register is available

Multiple LTC1658s may be daisy-chained together by

while the clock and CS/LD signals remain common to all

chips in the daisy chain. The serial data is clocked to all of

the chips then the CS/LD signal is pulled high to update all

of them simultaneously.

Voltage Output

The LTC1658 rail-to-rail buffered output can source or sink

5mA over the entire operating temperature range while

pulling to within 400mV of the positive supply voltage or

ground. The output swings to within a few millivolts of ei-

ther supply rail when unloaded and has an equivalent out-

put resistance of 40

rails. The output can drive 1000pF without going into os-

cillation.

The output swings from 0V to the voltage at the REF pin,

See Applications Information.