8

LTC1536

narrow (100

µs typ) soft reset pulse is generated on the

SRST output pin after the button is released. The push-

button circuitry contains an internal debounce counter

which delays the output of the soft reset pulse by typically

20ms. This pin can be OR-tied to the RST pin and issue

what is called a “soft” reset. The SRST thereby resets the

microprocessor without interrupting the DRAM refresh

cycle. In this manner DRAM information remains undis-

turbed. Alternatively, SRST may be monitored by the

processor to initiate a software-controlled reset.

a standard reset is generated. Once the 2-second period

has elapsed, a reset signal is produced by the pushbutton

logic, thereby clearing the reset counter. Once the PBR

pin is released, the reset counter begins counting the

reset period (200ms nominal). Consequently, the reset

outputs remain asserted for approximately 200ms after

the button is released.

Fast Undervoltage for PCI Applications

The LTC1536 is designed for PCI Local Bus applications

that require reset to be asserted quickly in response to one

or both of the power supply rails (5V and 3.3V) going out

margin to give the designer the ability to add follow-on

be used to monitor the “power good” signal and keep reset

applied until both supplies are in spec and the power good

signal is high.

Glitch Immunity and Fast Undervoltage Detection

The LTC1536 achieves its high speed characteristics while

maintaining glitch immunity by using two sets of com-

comparators set at different thresholds. A slow, very

accurate comparator monitors the supply for precision

undervoltage detection. In parallel, but with a threshold

250mV lower than the precision threshold, is a very fast

comparator that detects when the supply is quickly going

out of specification. Because the fast comparator thresh-

old is set 250mV above the PCI specification, typical

3V or 5V Power Detect/Gate Drive

The LTC1536 for the most part is powered internally from

FET on the RST pin. On the gate to this FET is power detect

circuitry used to detect and drive the gate from either the

3.3V pin or the 5V pin, whichever pin has the highest

potential. This ensures the part pulls the RST pin low as

soon as either input pin is

≥1V.

Extended ESD Tolerance of the PBR Input Pin

The PBR pin is susceptible to ESD since it can be brought

out to a front panel in normal applications. The ESD

tolerance of this pin can be increased by adding a resistor

in series with the PBR pin. A 10k resistor can increase the

ESD tolerance of the PBR pin to approximately 10kV. The

PBR’s internal pull-up current of 7

µA typical means there

is only 70mV (150mV max) dropped across the resistor.

1

2

3

4

8

7

6

5

GND

PBR

SRST

RST

RST

LTC1536

PCI

LOCAL

BUS

0.1

µF

3.3V SUPPLY

RESET

5V SUPPLY

1536 TA08

0.1

µF

ONBOARD

DEVICE

PCI Expansion Board RST Generation

Monitoring “Power Good”)

1

2

3

4

8

7

6

5

GND

PBR

SRST

RST

RST

LTC1536

3.3V

SYSTEM RESET

5V

PWR GOOD

1536 TA04