8

LTC1531

The zero-cross comparator inputs, ZCPOS and ZCNEG,

have an input common mode range that allows signal

swings near the positive supply rails. The ZCPOS and

ZCNEG inputs contain ESD diode protection devices which

will clamp input signals that go below GND. The current

into the diode should be limited to less than 5mA. The

Isolated Thermistor Temperature Controller shows an

example phase shift network with attenuation that satis-

fies these conditions. The positive input voltage should

not exceed the 12V maximum rating or the 5mA input

current to the ESD diode clamp.

ISOLATION dV/dt

The maximum continuous dV/dt across the isolation bar-

rier that will still allow the isolated comparator to operate

is 50V/

µs. Continuous rates of dV/dt greater than this

cause the isolated side to not detect when its power cycle

has stopped and a comparison should begin. Figure 4

shows the maximum continuous rate trade-off of fre-

quency vs voltage of a sine wave:

SR = (

f = frequency. Noise immunity to intermittent dV/dt rates

greater than 50V/

µs can be rejected by the LTC1531.

AC Noise Rejection and Things to Avoid

Minimizing AC noise pickup at the isolated comparator

should follow the following guidelines.

1. Allow the isolated side ground to float. The isolated side

should only be common with the isolated circuit.

2. Use hysteresis to decrease sensitivity by using CMPOUT.

since this output does not go Hi-Z (high impedance)

during the off time.

PC Board Layout

The PC board layout should not have copper near the lead

frame isolation capacitors. The copper reduces the power

coupling and power delivery to the isolated side (see

Figure 6).

TYPICAL APPLICATIONS DESCRIPTION

The Isolated Thermistor Temperature Controller (front

page) uses a simple AC power rectifier and Zener to

provide 5.6V of DC power to the LTC1531. To avoid power

dissipation in the 3k, 3W resistor, DC power can be

provided with a charge pump circuit similar to the Isolated

Switch Control. In this circuit, a thermistor half bridge is

used with the 4-input comparator connected to provide

the other half of the bridge, V4 = 2.5V, V3 = 0V, giving

(V4 + V3)/2 = 1.25V. With the 50k pot set to about 30k, the

trip point is 25

turns on and powers the half-bridge while the comparator

samples the result. The zero-cross comparator, ZCPOS

and ZCNEG, is used to trigger a triac at the 10

°phasepoint.

The circuit, R1, R2 and C1, provides the phase shift,

θ, as

determined by:

R2C1

≅ tan(θ)/2π60Hz

and where the attenuation

≅ R2/R1. In this example,

R1 = 680k, R2 = 47k and C1 = 0.01

µF, provide a 7V peak

input signal with 10

° of phase lag.

Figure 6. PC Board Layout Consideration

1

2

3

4

11

12

13

14

28

27

26

25

18

17

16

15

SHDN

ZCNEG

ZCPOS

CMPOUT

ISOGND

GND

ZCDATA

DATA

VALID

ETCH COPPER

FROM THE

SHADED AREA

V1

V2

V3

V4

SW PACKAGE

28-LEAD PLASTIC SO (ISO)

TOP VIEW

1531 F06