9

LTC1482

FU CTIO TABLES

Driver Enabled (DE = 1)

DI/SHDN

A

B

RO

CD

00

1

0

0

11

0

1

0

X

A Shorted to B

1

1

Driver Disabled (DE = 0, Notes 1, 2)

DI/SHDN

A – B

RO

CD

0

X (Note 3)

Z

1 (Internal Pull-Up)

11

1

A and B are Open

1

1

1

A and B are Shorted

1

1

00

and (A – B)

10

and (A – B)

X = Don’t Care

Z = High Impedance

alive except in shutdown.

Note 2: The table is valid regardless of the presence of an external

termination resistor.

Note 3: Although the RO and the driver outputs are three-stated, the A and

B pins each present a 22k

Ω receiver input resistance to ground.

TEST CIRCUITS

RECEIVER

OUTPUT

1k

S1

S2

TEST POINT

1k

1482 F03

A

B

R

R

1482 F01

Figure 1. Driver DC Test Load #1

Figure 3. Receiver Timing Test Load

A

B

375

Ω

375

Ω

60

Ω

–7V TO 12V

1482 F02

Figure 2. Driver DC Test Load #2

Figure 5. Driver Timing Test Load

OUTPUT

UNDER TEST

S1

S2

500

Ω

1482 F05

Figure 4. Driver/Receiver Timing Test Load

DE

A

B

DI

RO

CD

1k

15pF

A

B

1482 F04

(DE = 0, DI/SHDN = 0) or to disable the driver while keeping

the receiver alive (DE = 0, DI/SHDN = 1). When the driver

is enabled (DE = 1), DI/SHDN = 0 forces the A output low

and the B output high. DI/SHDN = 1 forces the A output

high and the B output low.

GND (Pin 5): Ground.

A (Pin 6): Driver Output/Receiver Input. The input resis-

tance is typically 22k when the driver is disabled (DE = 0).

When the driver is enabled, the A output follows the logic

level at the DI/SHDN pin.

B (Pin 7): Driver Output/Receiver Input. The input resis-

tance is typically 22k when the driver is disabled (DE = 0).

When the driver is enabled, the B output is inverted from

the logic level at the DI/SHDN pin.

bypass capacitor is recommended.