LTC1435CS datasheet(15/20 Pages) LINER

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LTC1435

APPLICATIONS INFORMATION

Design Example

As a design example, assume VIN = 12V(nominal), VIN =

22V(max), VOUT = 3.3V, IMAX = 3A and f = 250kHz, RSENSE

and COSC can immediately be calculated:

RSENSE = 100mV/3A = 0.033Ω

COSC = 1.37(10

4)/250 – 11 = 43pF

Referring to Figure 3, a 10

µH inductor falls within the

recommended range. To check the actual value of the

ripple current the following equation is used:

∆I

OUT

= ()( )









1–

The highest value of the ripple current occurs at the

maximum input voltage:

∆I

kHz

L =

()









250

–

.2A

The power dissipation on the topside MOSFET can be

easily estimated. Choosing a Siliconix Si4412DY results

in: RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input

voltage with T(estimated) = 50

°C:

kHz

MAIN =

() +() °− °

()

[]()

() ( )( )(

0 005 50

0 042

2 5 22

100

250

122

185

Ω

The most stringent requirement for the synchronous

N-channel MOSFET occurs when VOUT = 0 (i.e. short

circuit). In this case the worst-case dissipation rises to:

SYNC

SC AVG

DS ON

() +

()

( )

With the 0.033

Ω sense resistor ISC(AVG) = 4A will result,

increasing the Si4412DY dissipation to 950mW at a die

temperature of 105

°C.

CIN is chosen for an RMS current rating of at least 1.5A at

temperature. COUT is chosen with an ESR of 0.03Ω for low

output ripple. The output ripple in continuous mode will be

highest at the maximum input voltage. The output voltage

ripple due to ESR is approximately:

VORIPPLE = RESR(∆IL) = 0.03Ω(1.112A) = 34mVP-P

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1435. These items are also illustrated graphically in

the layout diagram of Figure 8. Check the following in your

layout:

1. Are the signal and power grounds segregated? The

LTC1435 signal ground pin must return to the (–) plate

of COUT. The power ground connects to the source of

the bottom N-channel MOSFET, anode of the Schottky

diode, and (–) plate of CIN, which should have as short

lead lengths as possible.

2. Does the VOSENSE pin connect directly to the feedback

resistors? The resistive divider R1, R2 must be con-

nected between the (+) plate of COUT and signal ground.

The 100pF capacitor should be as close as possible to

the LTC1435.

3. Are the SENSE– and SENSE+ leads routed together with

minimum PC trace spacing? The filter capacitor be-

tween SENSE+ and SENSE – should be as close as

possible to the LTC1435.

4. Does the (+) plate of CIN connect to the drain of the

topside MOSFET(s) as closely as possible? This capaci-

tor provides the AC current to the MOSFET(s).

5. Is the INTVCC decoupling capacitor connected closely

between INTVCC and the power ground pin? This ca-

pacitor carries the MOSFET driver peak currents.

6. Keep the switching node SW away from sensitive small-

signal nodes. Ideally the switch node should be placed

at the furthest point from the LTC1435.

7. SGND should be exclusively used for grounding exter-

nal components on COSC, ITH, VOSENSE and SFB pins.

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