UPD7564 datasheet(21/56 Pages) NEC

21 / 56 page

µPD7564A, 7564A(A)

2.12 SERIAL INTERFACE

The serial interface consists of an 8-bit shift register, 3-bit shift mode register, and 3-bit counter. It is used for

input/output of serial data.

Fig. 2-13 Serial Interface Block Diagram

INT0

P00/INT0

P01/SCK

P02/SO

P03/SI

*IPL

*TSIOAM

TAMSIO*

LSB

8–BIT SHIFT REG

MSB

3–BIT CNT

RS F/F

INTS

SIO*

SM3

SHIFT MODE REG

OPL*

Internal Bus

Instruction execution

Remarks

φ indicates the internal clock signal (system clock).

SM3 and INT0 go to the test control circuit.

Input/output of serial data is controlled by the serial clock. The highest bit (bit 7) of the shift register is output

from the SO line at rise of the serial clock (SCK pin signal). At its fall, the contents of the shift register is shifted by

one bit (bit n

→ bit n+1) and data on the SI line is loaded to the lowest bit (bit 0) of the shift register.

The 3-bit counter (octal counter) counts serial clock pulses. Wthenever it counts eight clock pulses (on completion

of 1-byte serial data transfer), the counter generates an internal test request signal INTS to set the test request flag

(INT0/S RQF).

Fig. 2-14 Shift Timing

INTS RQF

Setting Timing

SCK

DI7

DO7

MSB

DO6

DO5

DO4

DO3

DO2

DO1

DO0

DI6

DI5

DI4

DI3

DI2

DI1

DI0

LSB

Remarks

DI: Serial data input

DO: Serial data output

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