LTC1298CS8 datasheet(13/24 Pages) LINER

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LTC1286/LTC1298

APPLICATION INFORMATION

SAMPLE RATE (kHz)

0.1k

100

1000

10k

100k

LT1286/98 G03

TA = 25°C

VCC = VREF = 5V

fCLK = 200kHz

LTC1286

LTC1298

input becomes high impedance at the end of each conver-

sion leaving the CLK running to clock out the LSB first data

or zeroes (see Figures 1 and 2). If the CS is not running rail-

to-rail, the input logic buffer will draw current. This current

may be large compared to the typical supply current. To

obtain the lowest supply current, bring the CS pin to

ground when it is low and to supply voltage when it is high.

When the CS pin is high (= supply voltage), the converter

is in shutdown mode and draws only leakage current. The

status of the DIN and CLK input have no effect on supply

current during this time. There is no need to stop DIN and

CLK with CS = high; they can continue to run without

drawing current.

Minimize CS Low Time

In systems that have significant time between conver-

sions, lowest power drain will occur with the minimum CS

low time. Bringing CS low, transferring data as quickly as

possible, and then bringing it back high will result in the

lowest current drain. This minimizes the amount of time

the device draws power. After a conversion the ADC

automatically shuts down even if CS is held low (see

Figures 1 and 2). If the clock is left running to clock out

LSB-data or zero, the logic will draw a small current.

Figure 5 shows that the typical supply current with CS =

ground varies from 1

µA at 1kHz to 35µA at 200kHz. When

CS = VCC, the logic is gated off and no supply current is

drawn regardless of the clock frequency.

Shutdown

The LTC1286/LTC1298 are equipped with automatic shut-

down features. They draw power when the CS pin is low

and shut down completely when that pin is high. The bias

circuit and comparator powers down and the reference

ACHIEVING MICROPOWER PERFORMANCE

With typical operating currents of 250

µA and automatic

shutdown between conversions, the LTC1286/LTC1298

achieves extremely low power consumption over a wide

range of sample rates (see Figure 4). The auto-shutdown

allows the supply curve to drop with reduced sample rate.

Several things must be taken into account to achieve such

a low power consumption.

Figure 4. Automatic Power Shutdown Between Conversions

Allows Power Consumption to Drop with Sample Rate.

CLK

DATA (DIN/DOUT)

START

SGL/DIFF

ODD/SIGN

MSBF

B11

B10

•••

MSBF BIT LATCHED

BY LTC1298

LTC1298 CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO MPU

MPU CONTROLS DATA LINE AND SENDS

MUX ADDRESS TO LTC1298

PROCESSOR MUST RELEASE

DATA LINE AFTER 4TH RISING CLK

AND BEFORE THE 4TH FALLING CLK

LTC1298 TAKES CONTROL OF DATA LINE

ON 4TH FALLING CLK

LTC1286/98 F03

Figure 3. LTC1298 Operation with DIN and DOUT Tied Together

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