LTC1297BC datasheet(22/24 Pages) LINER

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LTC1292/LTC1297

APPLICATI

I FOR ATIO

LSB

(B0)

LSB-FIRST DATA

(B1)

MSB

(B11)

NULL

BIT

VERTICAL: 5V/DIV

HORIZONTAL: 2

µs/DIV

CLK

OUT

A “Quick Look” Circuit for the LTC1297

A circuit similar to the one used for the LTC1292 can be

used for the LTC1297(Figure 28). A one shot has been

generated with NAND gates, a resistor and capacitor to

satisfy the setup time tsuCS. This can be eliminated if a

slower clock is used. When CS goes low the one shot is

triggered. This turns off the clock to the LTC1297 for a

fixed time to meet tsuCS. Once the clock starts DOUT is

shifted out one bit at a time. CS is driven at 1/64 the

clock rate by the 74HC393. The output data from the

DOUT pin can be viewed on an oscilloscope that is set to

trigger on the falling edge of CS. See Figure 29.

CLK

OUT

NULL

BIT

MSB

(B11)

LSB-FIRST DATA

(B1)

LSB

(B0)

VERTICAL: 5V/DIV

HORIZONTAL: 5

µs/DIV

Figure 29. Scope Trace of the LTC1297 “Quick Look”

Circuit Showing A/D Output 101010101010 (AAAHEX)

Figure 27. Scope Trace of the LTC1292 “Quick Look”

Circuit Showing A/D Output 101010101010 (AAAHEX)

Figure 28. “Quick Look” Circuit for the LTC1297

TO OSCILLOSCOPE

LTC1292/7 F28

0.1µF

VIN

f/64

340

Ω

22µF

TANTALUM

VCC

CLK

DOUT

VREF

+IN

–IN

GND

LTC1297

74HC393

CLR1

1QA

1QB

1QC

1QD

GND

VCC

CLR2

2QA

2QB

2QC

2QD

0.02

µF

CLOCK IN 1MHz

A “Quick Look” Circuit for the LTC1292

Users can get a quick look at the function and timing of

the LTC1292 by using the “Quick Look” circuit in Figure

26. VREF is tied to VCC. VIN is applied to the +IN input

and the –IN input is tied to the ground plane. CS is driven

at 1/32 the clock rate by the CD4520 and DOUT outputs

the data. The output data from the DOUT pin can be

viewed on an oscilloscope that is set up to trigger on the

falling edge of CS (Figure 27). Note the LSB data is

partially clocked out before CS goes high.

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