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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LTC1289CC датащи(PDF) 3 Page - Linear Technology |
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LTC1289CC датащи(HTML) 3 Page - Linear Technology |
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3 / 28 page  3 LTC1289 LTC1289B LTC1289C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCLK Shift Clock Frequency (Note 6) 0 1.0 MHz fACLK A/D Clock Frequency (Note 6) (Note 10) 2.0 MHz tACC Delay time from CS ↓ to DOUT Data Valid (Note 9) 2 ACLK Cycles tSMPL Analog Input Sample Time See Operating Sequence 7 SCLK Cycles tCONV Conversion Time See Operating Sequence 52 ACLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) 12 SCLK + Cycles 56 ACLK tdDO Delay Time, SCLK ↓ to DOUT Data Valid See Test Circuits q 200 350 ns tdis Delay Time, CS ↑ to DOUT Hi-Z See Test Circuits q 70 150 ns ten Delay Time, 2nd ACLK ↓ to DOUT Enabled See Test Circuits q 130 250 ns thCS Hold Time, CS After Last SCLK ↓ (Note 6) 0 ns thDI Hold Time, DIN After SCLK ↑ (Note 6) 50 ns thDO Time Output Data Remains Valid After SCLK ↓ 50 ns tf DOUT Fall Time See Test Circuits q 40 100 ns tr DOUT Rise Time See Test Circuits q 40 100 ns tsuDI Setup Time, DIN Stable Before SCLK ↑ (Note 6 and 9) 50 ns tsuCS Setup Time, CS ↓ Before Clocking in (Note 6 and 9) 2 ACLK Cycles First Address Bit + 180ns tWHCS CS High Time During Conversion (Note 6) 52 ACLK Cycles CIN Input Capacitance Analog Inputs On Channel 100 pF Analog Inputs Off Channel 5 pF Digital Inputs 5 pF (Note 3) AC CHARACTERISTICS |
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