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LTC1287BC датащи(PDF) 2 Page - Linear Technology

номер детали LTC1287BC
подробное описание детали  3V Single Chip 12-Bit Data Acquisition System
PDF  16 Pages
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

LTC1287BC датащи(HTML) 2 Page - Linear Technology

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LTC1287
PACKAGE/ORDER I FOR ATIO
A
G
A
U
A
R
BSOLUTEXI
TI
S
(Notes 1 and 2)
Supply Voltage (VCC) to GND.................................. 12V
Voltage
Analog and Reference Inputs .... –0.3V to VCC + 0.3V
Digital Inputs ........................................ –0.3V to 12V
Digital Outputs .......................... –0.3V to VCC + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1287BI, LTC1287CI ................... – 40
°C TO 85°C
LTC1287BC, LTC1287CC ....................... 0
°C to 70°C
Storage Temperature Range ................ –65
°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300
°C
ORDER PART
NUMBER
LTC1287BIJ
LTC1287CIJ
LTC1287BIN
LTC1287CIN
LTC1287BCJ
LTC1287CCJ
LTC1287BCN
LTC1287CCN
1
2
3
45
6
7
8
TOP VIEW
J8 PACKAGE
8-LEAD CERAMIC DIP
VCC
CLK
DOUT
VREF
CS
+IN
–IN
GND
1287 PO
N8 PACKAGE
8-LEAD PLASTIC DIP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Offset Error
VCC = 2.7V (Note 4)
q
±3.0
±3.0
LSB
Linearity Error (INL)
VCC = 2.7V (Notes 4 & 5)
q
±0.5
±0.5
LSB
Gain Error
VCC = 2.7V (Note 4)
q
±0.5
±1.0
LSB
Minimum Resolution for Which No
q
12
12
Bits
Missing Codes are Guaranteed
Analog and REF Input Range
(Note 7)
V
On Channel Leakage Current (Note 8)
On Channel = 3V
q
±1
±1
µA
Off Channel = 0V
On Channel = 0V
q
±1
±1
µA
Off Channel = 3V
Off Channel Leakage Current (Note 8)
On Channel = 3V
q
±1
±1
µA
Off Channel = 0V
On Channel = 0V
q
±1
±1
µA
Off Channel = 3V
LTC1287B
LTC1287C
(Note 3)
CO VERTER A D
ULTIPLEXER CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fCLK
Clock Frequency
(Note 6)
(Note 9)
0.5
MHz
tSMPL
Analog Input Sample Time
See Operating Sequence
1.5
CLK Cycles
tCONV
Conversion Time
See Operating Sequence
12
CLK Cycles
tCYC
Total Cycle Time
See Operating Sequence (Note 6)
14 CLK+
Cycles
5.0
µs
tdDO
Delay Time, CLK
↓ to DOUT Data Valid
See Test Circuits
q
250
450
ns
tdis
Delay Time, CS
↑ to DOUT Hi-Z
See Test Circuits
q
80
160
ns
ten
Delay Time, CLK
↓ to DOUT Enabled
See Test Circuits
q
130
250
ns
AC CHARACTERISTICS (Note 3)
LTC1287B/LTC1287C
(V –) – 0.05V to VCC + 0.05V



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