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UPD75P0076CU датащи(PDF) 39 Page - NEC |
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UPD75P0076CU датащи(HTML) 39 Page - NEC |
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39 / 62 page ![]() µPD75P0076 39 AC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Symbol Test conditions MIN. TYP. MAX. Unit CPU clock cycle tCY Operating on VDD = 2.7 to 5.5 V 0.67 64 µs time Note 1 main system clock 0.95 64 µs (Minimum instruction execution Operating on 114 122 125 µs time = 1 machine cycle) subsystem clock TI0, TI1 input fTI VDD = 2.7 to 5.5 V 0 1.0 MHz frequency 0 275 kHz TI0, TI1 input tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 µs high-/low-level width 1.8 µs Interrupt input high-/ tINTH, tINTL INT0 IM02 = 0 Note 2 µs low-level width IM02 = 1 10 µs INT1, 2, 4 10 µs KR0 to KR3 10 µs RESET low-level width tRSL 10 µs Notes 1. The cycle time (minimum instruction execution time) of the CPU clock ( Φ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fx is set by setting the interrupt mode register (IM0). 1 02 3 4 5 6 0.5 1 3 2 4 5 6 60 64 Supply Voltage VDD [V] tCY vs VDD (At main system clock operation) Guaranteed Operation Range |
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