LTC1257CS8 datasheet(5/12 Pages) LINER

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LTC1257

TYPICAL PERFORMANCE CHARACTERISTICS

CL (µF)

0.01

0.1

1257 G11

100

Reference Compensation

Resistance vs CL

Broadband Noise

PI FU CTIO S

GND (Pin 5): Ground.

REF (Pin 6): The output of the 2.048V reference and the

input to the DAC resistor ladder. An external reference with

voltage from 2.475V to VCC – 2.7V may be used to override

the internal reference.

VOUT (Pin 7): The buffered DAC output is capable of

sourcing 2mA over temperature while pulling within 2.7V

of VCC. The output will pull to ground through an internal

200

Ω equivalent resistance.

VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤

15.75V. Requires a bypass capacitor to ground.

CLK (Pin 1): The TTL level input for the serial interface

clock.

DIN(Pin 2): The TTL level input for the serial interface data.

Data on the DIN pin is latched into the shift register on the

rising edge of the serial clock.

LOAD (Pin 3): The TTL level input for the serial interface

load control. Data is loaded from the shift register into the

DAC register, thus updating the DAC output when LOAD is

pulled low. The DAC register is transparent as long as

LOAD is held low.

DOUT(Pin 4):

The output of the shift register which

becomes valid on the rising edge of the serial clock. The

DOUT pin is driven from GND to VCC by an internal CMOS

inverter. Multiple LTC1257s may be cascaded by connect-

ing the DOUT pin to the DIN pin of the next chip.

CODE

0.5

0.0

–0.5

1024

2048 2560

1257 TA05

512

1536

3072 3584 4098

Differential Nonlinearity (DNL)

TIME = 5ms/DIV

1257 G12

CODE = FFFH

BW = 3Hz TO 1MHz

GAIN = 1100

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