11

LTC1235

S

APPLICATI

I FOR ATIO

Table 1 shows the state of each pin during battery backup.

IN and CE OUT, control the Chip Enable or Write inputs of

high, independent of CE IN. CE OUT is an alternative signal

to drive the CE, CS, or Write input of battery-backed up

CMOS RAM. CE OUT can also be used to drive the Store

or Write input of an EEPROM, EAROM or NOVRAM to

achieve similar protection. Figure 6 shows the timing

diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor’s address

decoder output. Figure 7 shows a typical nonvolatile

CMOS RAM application.

Figure 6. Timing Diagram for CE IN and CE OUT

SIGNAL

STATUS

BACKUP

BACKUP is ignored.

The supply current is 1

µA maximum.

BATT ON

PFI

Power Failure Input is ignored.

PFO

Logic low

PB RST

PB RST is ignored.

RESET

Logic low

RESET

LOW LINE Logic low

WDI

Watchdog Input is ignored.

WDO

CE IN

Chip Enable Input is ignored.

CE OUT

Table 1. Input and Output Status in Battery Backup Mode

Memory Protection

The LTC1235 includes memory protection circuitry which

ensures the integrity of the data in memory by preventing

+5V

+3V

0.1µF

10µF

LTC1235

GND

LTC1235 F06

RESET

CE IN

CE OUT

BACKUP

0.1µF

TO µP

FROM DECODER

CS

20ns PROPAGATION DELAY

62512

RAM

+

GND

Figure 7. A Typical Nonvolatile CMOS RAM Application

V1

CE IN

V2

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

LTC1235 F06

CE OUT