LTC1196 datasheet(17/28 Pages) LINER

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LTC1196/LTC1198

APPLICATI

I FOR ATIO

Figure 4. LTC1198 Operation with DIN and DOUT Tied Together

SAMPLE RATE (Hz)

0.01

0.1

100

10k

100k

1196/98 F05

0.001

LT1196 VCC = 5V

LT1196 VCC = 2.7V

LT1198 VCC = 5V

LT1198 VCC = 2.7V

Figure 5. Supply Current vs Sample Rate for LTC1196/

LTC1198 Operating on 5V and 2.7V Supplies

Minimize CS Low Time (LTC1198)

In systems that have significant time between conver-

sions, lowest power drain will occur with the minimum CS

low time. Bringing CS low, transfering data as quickly as

possible, then bringing it back high will result in the lowest

current drain. This minimizes the amount of time the

device draws power.

OPERATING ON OTHER THAN 5V SUPPLIES

The LTC1196/LTC1198 operate from single 2.7V to 6V

supplies. To operate the LTC1196/LTC1198 on other than

5V supplies, a few things must be kept in mind.

Input Logic Levels

The input logic levels of CS, CLK and DIN are made to

meet TTL on 5V supply. When the supply voltage varies,

the input logic levels also change (see typical curve of

Digital Input Logic Threshold vs Supply Voltage). For

these two ADCs to sample and convert correctly, the

digital inputs have to be in the logical low and high relative

to the operating supply voltage. If achieving micropower

consumption is desirable on the LTC1198, the digital

inputs must go rail-to-rail between supply voltage and

ground (see Reducing Power Consumption section).

When the CS pin is high (= supply voltage), the LTC1198

is in shutdown mode and draws only leakage current. The

status of the DIN and CLK input has no effect on the supply

current during this time. There is no need to stop DIN and

CLK with CS = high; they can continue to run without

drawing current.

CLK

DATA (DIN/DOUT)

START

SGL/DIFF

ODD/SIGN

DUMMY

DUMMY BITS LATCHED

BY LTC1198

LTC1198 CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO THE DIGITAL SYSTEM

THE DIGITAL SYSTEM CONTROLS DATA LINE

AND SENDS MUX ADDRESS TO LTC1198

THE DIGITAL SYSTEM MUST RELEASE

DATA LINE AFTER 5TH RISING CLK

AND BEFORE THE 5TH FALLING CLK

LTC1198 TAKES CONTROL OF

DATA LINE ON 5TH FALLING CLK

1196/98 F04

DUMMY

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