LTC1148CS datasheet(15/20 Pages) LINER

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LTC1148

LTC1148-3.3/LTC1148-5

Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1148 series. These items are also illustrated graphi-

cally in the layout diagram of Figure 9. Check the following

in your layout:

1. Are the signal and power grounds segregated? The

LTC1148 signal ground Pin 11 must return to the (–)

plate of COUT. The power ground returns to the

source of the N-channel MOSFET, anode of the

Schottky diode, and (–) plate of CIN, which should

have as short lead lengths as possible.

2. Does the LTC1148 SENSE – Pin 7 connect to a point

close to RSENSE and the (+) plate of COUT? In adjust-

able applications, the resistive divider R1, R2 must be

connected between the (+) plate of COUT and signal

ground.

3. Are the SENSE – and SENSE + leads routed together

with minimum PC trace spacing? The 1000pF capacitor

between Pins 7 and 8 should be as close as possible to

the LTC1148.

4. Does the (+) plate of CIN connect to the source of the

P-channel MOSFET as closely as possible? This capaci-

tor provides the AC current to the P-channel MOSFET.

5. Is the 1

µF VIN decoupling capacitor connected closely

between Pin 3 and power ground Pin 12? This capacitor

carries the MOSFET driver peak currents.

6. Is the Shutdown Pin 10 actively pulled to ground during

normal operation? The Shutdown pin is high imped-

ance and must not be allowed to float.

Figure 9. LTC1148 Layout Diagram (See Board Layout Checklist)

APPLICATIO S I FOR ATIO

COUT

µF

P-CHANNEL

3300pF

10nF

LTC1148

RSENSE

N-CHANNEL

CIN

–

VOUT

VIN

OUTPUT DIVIDER REQUIRED WITH

ADJUSTABLE VERSION ONLY

BOLD LINES INDICATE HIGH CURRENT PATHS

LTC1148 • F09

SHUTDOWN

1000pF

P-DRIVE

VIN

INTVCC

ITH

SENSE–

N-DRIVE

PGND

SGND

SHDN

NC (VFB)

SENSE+

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