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LTC1090

1090fc

3. Analog Inputs

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1090 have

capacitive switching input current spikes. These current

spikes settle quickly and do not cause a problem.

However, if large source resistances are used or if slow

settling op amps drive the inputs, care must be taken to

insure that the transients caused by the current spikes

settle completely before the conversion begins.

Source Resistance

The analog inputs of the LTC1090 look like a 60pF capaci-

tor (CIN) in series with a 500Ω resistor (RON) as shown in

Figure 9. CIN gets switched between the selected “+” and

“–” inputs once during each conversion cycle. Large

external source resistors and capacitances will slow the

settling of the inputs. It is important that the overall RC

time constants be short enough to allow the analog inputs

to completely settle within the allowed time.

APPLICATIO S I FOR ATIO

Figure 9. Analog Input Equivalent Circuit

“+” Input Settling

This input capacitor is switched onto the “+” input during

the sample phase (tSMPL, see Figure 10). The sample

phase starts at the 4th SCLK cycle and lasts until the falling

edge of the last SCLK (the 8th, 10th, 12th or 16th SCLK

cycle depending on the selected word length). The voltage

on the “+” input must settle completely within this sample

time. Minimizing RSOURCE+ and C1 will improve the input

settling time. If large “+” input source resistance must be

used, the sample time can be increased by using a slower

SCLK frequency or selecting a longer word length. With

the minimum possible sample time of 4µs, RSOURCE+ < 2k

and C1 < 20pF will provide adequate settling.

“–” Input Settling

At the end of the sample phase the input capacitor switches

to the “–” input and the conversion starts (see Figure 10).

During the conversion, the “+” input voltage is effectively

“held” by the sample and hold and will not affect the

conversion result. However, it is critical that the “–” input

voltage be free of noise and settle completely during the

first four ACLK cycles of the conversion time. Minimizing

RSOURCE– and C2 will improve settling time. If large

“–” input source resistance must be used, the time allowed

for settling can be extended by using a slower ACLK

frequency. At the maximum ACLK rate of 2MHz, RSOURCE–

< 1kΩ and C2 < 20pF will provide adequate settling.

Figure 10. “+” and “–” Input Settling Windows

LTC1090 • AI17

SCLK

ACLK

t SMPL

HOLD

1ST BIT

TEST

LAST SCLK (8TH, 10TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)

“ – ” INPUT MUST SETTLE

DURING THIS TIME

“ + ” INPUT MUST

SETTLE DURING THIS TIME

SAMPLE

MUX ADDRESS

SHIFTED IN

“ – ” INPUT

“ + ” INPUT

LTC1090 • AI16

RSOURCE+

RSOURCE–

VIN–

VIN+

4TH SCLK

LAST SCLK

RON = 500Ω

CIN = 60pF

LTC1090

“

– ”

INPUT

“

+ ”

INPUT

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