4

LT1949

nect a series RC network from this pin to ground. Typical

values for compensation are a 68k/330pF combination

when using ceramic output capacitors. Minimize trace

FB (Pin 2): Feedback Pin. Reference voltage is 1.24V.

Connect resistor divider tap here. Minimize trace area at

SHDN (Pin 3): Shutdown. Pull this pin low for shutdown

mode (only the low-battery detector remains active).

Leave this pin floating or tie to a voltage between 1.4V and

6V to enable the device. SHDN pin is logic level and need

only meet the logic specification (1.4V for high, 0.4V for

low).

GND (Pin 4): Ground. Connect directly to local ground

plane.

SW (Pin 5): Switch Pin. Connect inductor/diode here.

Minimize trace area at this pin to keep EMI down.

pin.

LBI (Pin 7): Low-Battery Detector Input. 200mV refer-

ence. Voltage on LBI must stay between ground and

700mV. Low-battery detector remains active in shutdown

mode.

LBO (Pin 8): Low-Battery Detector Output. Open collec-

tor, can sink 10

µA. A 1MΩ pull-up is recommended.

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

50mV/DIV

DC

COUPLED

OFFSET

ADDED

L1 = 10

µH, SUMIDA CD54

1949 G10

Load Regulation

50mV/DIV

DC

COUPLED

OFFSET

ADDED

L1 = 10

µH, SUMIDA CD54

1949 G11

Transient Response

100mV/DIV

AC COUPLED

50

µs/DIV

CIRCUIT OF FIGURE 1

1949 G12

500mA/DIV

200mA

100mA

TEMPERATURE (

°C)

–50

26

25

24

23

22

21

20

–25

0

25

50

1317 TPC10

75

100

TEMPERATURE (

°C)

–50

–25

0

25

50

75

100

1317 TPC11

40

36

32

28

24

20

16

12

8

4

0

Quiescent Current, SHDN = 0V

FB Pin Bias Current

SHDN Pin Current

SHDN PIN VOLTAGE (V)

0

3

5

1317 TPC12

12

4

2

1

0

–1

–2

–3

6

PI FU CTIO S