LT1787HVCMS8 datasheet(8/12 Pages) LINER

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LT1787/LT1787HV

APPLICATIONS INFORMATION

Kelvin connection of the LT1787’s VS+ and VS– inputs to

the sense resistor should be used in all but the lowest

power applications. Solder connections and PC board

interconnect resistance (approximately 0.5m

Ωpersquare)

can be a large error in high current systems. A 5-Amp

application might choose a 20m

Ω sense resistor to give a

100mV full-scale input to the LT1787. Input offset voltage

will limit resolution to 2mA. Neglecting contact resistance

at solder joints, even one square of PC board copper at

each resistor end will cause an error of 5%. This error will

grow proportionately higher as monitored current levels

rise to tens or hundreds of amperes.

Input Noise Filtering

The LT1787 provides input signal filtering pins FIL+ and

FIL– that are internally connected to the midpoint taps of

resistors RG1 and RG2. These pins may be used to filter the

input signal entering the LT1787’s internal amplifier, and

should be used when fast current ripple or transients may

flow through the sense resistor. High frequency signals

above the 300kHz bandwidth of the LT1787’s internal

amplifier will cause errors. A capacitor connected between

FIL+ and FIL– creates a single pole low pass filter with

corner frequency:

f–3dB = 1/(2πRC)

where R = 1.25k. A 0.01

µF capacitor creates a pole at

12.7kHz, a good choice for many applications.

Common mode filtering from the FIL+ and FIL– pins should

not be attempted, as mismatch in the capacitors from FIL+

and FIL– will create AC common mode errors. Common

mode filtering must be done at the power supply output.

Output Signal Range

The LT1787’s output signal is developed by summing the

net currents through RG1 and RG2 into output resistor

ROUT. The pins VOUT and VBIAS may be connected in

numerous configurations to interface with following cir-

cuitry in either single supply or split supply applications.

Care must be used in connecting the output pins to

preserve signal accuracy. Limitations on the signal swing

at VOUT are imposed by the negative supply, VEE, and the

input voltage VS+. In the negative direction, internal circuit

saturation with loss of accuracy occurs for VOUT < 70mV

with absolute minimum swing at 30mV above VEE. VOUT

may swing positive to within 0.75V of VS+ or a maximum

of 35V, a limit set by internal junction breakdown. Within

these contraints, an amplified, level shifted representation

of the RSENSE voltage is developed across ROUT.

Split Supply Bipolar Output Swing

Figure 2 shows the LT1787 used with split power supplies.

The VBIAS pin is connected to ground, and the output

signal appears at the VOUT pin. Bidirectional input currents

can be monitored with the output swinging positive for

current flow from VS+ and VS–. Input currents in the

opposite direction cause VOUT to swing below ground.

Figure 2 shows an optional output capacitor connected

from VOUT to ground. This capacitor may be used to filter

the output signal before it is processed by other

circuitry.Figure 3 shows the voltage transfer function of

the LT1787 used in this configuration.

Single Supply with Shifted VBIAS

Figure 4 shows the LT1787 used in a single supply mode

with the VBIAS pin shifted positive using an external

LT1634 voltage reference. The VOUT output signal can

swing above and below VBIAS to allow monitoring of

positive or negative currents through the sense resistor,

as shown in Figure 5. The choice of reference voltage is not

critical except for the precaution that adequate headroom

must be provided for VOUT to swing without saturating the

internal circuitry. The component values shown in Figure 4

allow operation with VS supplies as low as 3.1V.

Operation with A/D Converter

Figure 6 shows the LT1787 operating with the LTC1286

A/D converter. This low cost circuit is capable of 12-bit

resolution of unipolar currents. The – IN pin of the A/D

converter is biased at 1V by the resistor divider R1 and R2.

This voltage increases as sense current increases, with the

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