LT1776CS8 datasheet(12/20 Pages) LINER

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LT1776

APPLICATIONS INFORMATION

PAC = 1/2 • VIN • IOUT • (tr + tf + 30ns) • f

tr = (VIN/1.6)ns in high dV/dt mode

(VIN/0.16)ns in low dV/dt mode

tf = (VIN/1.6)ns (irrespective of dV/dt mode)

f = switching frequency

Total power dissipation of the die is simply the sum of

quiescent, DC and AC losses previously calculated.

PD(TOTAL) = PQ + PDC + PAC

Frequency Compensation

Loop frequency compensation is performed by connect-

ing a capacitor, or in most cases a series RC, from the

output of the error amplifier (VC pin) to ground. Proper

loop compensation may be obtained by empirical meth-

ods as described in detail in Application Note 19. Briefly,

this involves applying a load transient and observing the

dynamic response over the expected range of VIN and

ILOAD values.

As a practical matter, a second small capacitor, directly

from the VC pin to ground is generally recommended to

attenuate capacitive coupling from the VSW pin. A typical

value for this capacitor is 100pF. (See Switch Node Con-

siderations).

Switch Node Considerations

For maximum efficiency, switch rise and fall times are

made as short as practical. To prevent radiation and high

frequency resonance problems, proper layout of the com-

ponents connected to the IC is essential, especially the

power path. B field (magnetic) radiation is minimized by

keeping output diode, switch pin and input bypass capaci-

tor leads as short as possible. E field radiation is kept low

by minimizing the length and area of all traces connected

to the switch pin (VSW). A ground plane should always be

used under the switcher circuitry to prevent interplane

coupling.

However, remember that oscillator slowdown to achieve

short-circuit protection (discussed above) is dependent

on FB pin behavior, and this in turn, is sensitive to FB node

external impedance. Figure 2 shows the typical relation-

ship between FB divider Thevenin voltage and impedance,

and oscillator frequency. This shows that as feedback

network impedance increases beyond 10k, complete os-

cillator slowdown is not achieved, and short-circuit pro-

tection may be compromised. And as a practical matter,

the product of FB pin bias current and larger FB network

impedances will cause increasing output voltage error.

(Nominal cancellation for 10k of FB Thevenin impedance

is included internally.)

Thermal Considerations

Care should be taken to ensure that the worst-case input

voltage and load current conditions do not cause exces-

sive die temperatures. The packages are rated at 110

°C/W

for the 8-pin SO (S8) and 130

°C/W for 8-pin PDIP (N8).

Quiescent power is given by:

PQ = IIN • VIN + IVCC • VOUT

(This assumes that the VCC pin is connected to VOUT.)

Power loss internal to the LT1776 related to actual output

current is composed of both DC and AC switching losses.

These can be roughly estimated as follows:

DC switching losses are dominated by output switch “ON

voltage”, i.e.,

PDC = VON • IOUT • DC

VON = Output switch ON voltage, typically 1V at 500mA

IOUT = Output current

DC = ON duty cycle

AC switching losses are typically dominated by power lost

due to the finite rise time and fall time at the VSW node.

Assuming, for simplicity, a linear ramp up of both voltage

and current and a current rise/fall time equal to 15ns,

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