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LT1676CS8 датащи(PDF) 6 Page - Linear Technology |
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LT1676CS8 датащи(HTML) 6 Page - Linear Technology |
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6 / 16 page ![]() 6 LT1676 BLOCK DIAGRA SWDR SWDR SWON SWON BOOST 1676 BD BOOST SWOFF SWOFF LOGIC OSC BIAS VTH VB VBG VBG FB VC GND SYNC SHDN VCC FB AMP BOOST COMP gm I I I I R1 RSENSE I COMP Q4 Q3 Q2 Q1 Q5 VSW D1 VIN 5 3 2 1 6 4 8 7 OPERATIO The LT1676 is a current mode switching regulator IC that has been optimized for high efficiency operation in high input voltage, low output voltage Buck topologies. The Block Diagram shows an overall view of the system. Several of the blocks are straightforward and similar to those found in traditional designs, including: Internal Bias Regulator, Oscillator and Feedback Amplifier. The novel portion includes an elaborate Output Switch section and Logic Section to provide the control signals required by the switch section. The LT1676 operates much the same as traditional current mode switchers, the major difference being its specialized output switch section. Due to space con- straints, this discussion will not reiterate the basics of current mode switcher/controllers and the “Buck” topol- ogy. A good source of information on these topics is Application Note 19. Output Switch Theory One of the classic problems in delivering low output voltage from high input voltage at good efficiency is that minimizing AC switching losses requires very fast volt- age (dV/dt) and current (dI/dt) transition at the output device. This is in spite of the fact that in a bipolar implementation, slow lateral PNPs must be included in the switching signal path. Fast positive-going slew rate action is provided by lateral PNP Q3 driving the Darlington arrangement of Q1 and Q2. The extra β available from Q2 greatly reduces the drive requirements of Q3. Although desirable for dynamic reasons, this topology alone will yield a large DC forward voltage drop. A second lateral PNP, Q4, acts directly on the base of Q1 to reduce the voltage drop after the slewing phase has taken place. To achieve the desired high slew rate, PNPs Q3 and Q4 are “force-fed” packets of charge via the current sources controlled by the boost signal. |
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