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LT1506

APPLICATIONS INFORMATION

cases, the resistor may have to be larger to get acceptable

phase response, and some means must be used to control

ripple voltage at the VC pin. The suggested way to do this

is to add a capacitor (CF) in parallel with the RC/CC network

on the VC pin. Pole frequency for this capacitor is typically

set at one-fifth of switching frequency so that it provides

significant attenuation of switching ripple, but does not

add unacceptable phase shift at loop unity-gain frequency.

With RC = 3k,

= ()( )( )= 





 ()

500 10

531

•

How Do I Test Loop Stability?

The “standard” compensation for LT1506 is a 1.5nF

capacitor for CC, with RC = 0. While this compensation will

work for most applications, the “optimum” value for loop

compensation components depends, to various extent, on

parameters which are not well controlled. These include

inductor value (

±30% due to production tolerance, load

current and ripple current variations),

output capacitance

(

±20% to ±50% due to production tolerance, tempera-

ture, aging and changes at the load),

output capacitor ESR

(

±200% due to production tolerance, temperature and

aging), and finally,

DC input voltage and output load

current . This makes it important for the designer to check

out the final design to ensure that it is “robust” and tolerant

of all these variations.

I check switching regulator loop stability by pulse loading

the regulator output while observing transient response at

the output, using the circuit shown in Figure 13. The

regulator loop is “hit” with a small transient AC load

current at a relatively low frequency, 50Hz to 1kHz. This

causes the output to jump a few millivolts, then settle back

to the original value, as shown in Figure 14. A well behaved

loop will settle back cleanly, whereas a loop with poor

phase or gain margin will “ring” as it settles. The

number

of rings indicates the degree of stability, and the

frequency

of the ringing shows the approximate unity-gain fre-

quency of the loop.

Amplitude of the signal is not particu-

larly important, as long as the amplitude is not so high that

the loop behaves nonlinearly.

GMP = Transconductance of power stage = 5.3A/V

GMA = Error amplifier transconductance = 2(10–3)

ESR = Output capacitor ESR

2.42 = Reference voltage

With VOUT = 5V and ESR = 0.03Ω, a value of 6.5k for RC

would yield zero gain margin, so this represents an upper

limit. There is a second limitation however which has

nothing to do with theoretical small signal dynamics. This

resistor sets high frequency gain of the error amplifier,

including the gain at the switching frequency. If switching

frequency gain is high enough, output ripple voltage will

appear at the VC pin with enough amplitude to muck up

proper operation of the regulator. In the marginal case,

subharmonic switching occurs, as evidenced by alternat-

ing pulse widths seen at the switch node. In more severe

cases, the regulator squeals or hisses audibly even though

the output voltage is still roughly correct. None of this will

show on a theoretical Bode plot because Bode is an

amplitude insensitive analysis.

Tests have shown that if

ripple voltage on the VC is held to less than 100mVP-P, the

LT1506 will be well behaved. The formula below will give

an estimate of VC ripple voltage when RC is added to the

loop, assuming that RC is large compared to the reactance

of CC at 500kHz.

ESR

VL f

C RIPPLE

OUT

(

) =

()( ) −

()( )( )

GMA = Error amplifier transconductance (2000µMho)

If a computer simulation of the LT1506 showed that a

series compensation resistor of 3k gave best overall loop

response, with adequate gain margin, the resulting VC pin

ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω,

L = 10

µH, would be:

C RIPPLE

(

)

−

()





−

()( )( )

()













2 10

10 5 0 1 2 4

10 10 10

500 10

0 144

•.

••

This ripple voltage is high enough to possibly create

subharmonic switching. In most situations a compromise

value (< 2k in this case) for the resistor gives acceptable

phase margin and no subharmonic problems. In other

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