10

LT1354

Input Considerations

Each of the LT1354 inputs is the base of an NPN and

a PNP transistor whose base currents are of opposite

polarity and provide first-order bias current cancellation.

Because of variation in the matching of NPN and PNP

beta, the polarity of the input bias current can be positive

or negative. The offset current does not depend on

NPN/PNP beta matching and is well controlled. The use of

balanced source resistance at each input is recommended

for applications where DC accuracy must be maximized.

The inputs can withstand transient differential input volt-

ages up to 10V without damage and need no clamping or

source resistance for protection. Differential inputs, how-

ever, generate large supply currents (tens of mA) as

required for high slew rates. If the device is used with

sustained differential inputs, the average supply current

will increase, excessive power dissipation will result and

a comparator, peak detector or other open-loop applica-

normal, closed-loop operation, an increase of power

dissipation is only noticeable in applications with large

slewing outputs and is proportional to the magnitude of

the differential input voltage and the percent of the time

that the inputs are apart. Measure the average supply

current for the application in order to calculate the power

dissipation.

Power Dissipation

The LT1354 combines high speed and large output drive

in a small package. Because of the wide supply voltage

range, it is possible to exceed the maximum junction

temperature under certain conditions. Maximum junction

Worst case power dissipation occurs at the maximum

supply current and when the output voltage is at 1/2 of

either supply voltage (or the maximum swing if less than

Example: LT1354CS8 at 70

(Note: the minimum short-circuit current at 70

°C is

24mA, so the output swing is guaranteed only to 2.4V with

100

Ω.)

Circuit Operation

The LT1354 circuit topology is a true voltage feedback

amplifier that has the slewing behavior of a current feed-

back amplifier. The operation of the circuit can be under-

stood by referring to the simplified schematic. The inputs

are buffered by complementary NPN and PNP emitter

followers which drive an 800

Ω resistor. The input voltage

appears across the resistor generating currents which are

mirrored into the high impedance node. Complementary

followers form an output stage which buffers the gain

node from the load. The bandwidth is set by the input

resistor and the capacitance on the high impedance node.

The slew rate is determined by the current available to

charge the gain node capacitance. This current is the

differential input voltage divided by R1, so the slew rate

is proportional to the input. Highest slew rates are there-

fore seen in the lowest gain configurations. For example,

a 10V output step in a gain of 10 has only a 1V input step,

whereas the same output step in unity gain has a 10 times

greater input step. The curve of Slew Rate vs Input Level

illustrates this relationship. The LT1354 is tested for slew

rate in a gain of –2 so higher slew rates can be expected

in gains of 1 and –1, and lower slew rates in higher gain

configurations.

The RC network across the output stage is bootstrapped

when the amplifier is driving a light or moderate load and

has no effect under normal operation. When driving a

capacitive load (or a low value resistive load) the network

is incompletely bootstrapped and adds to the compensa-

tion at the high impedance node. The added capacitance