8

LT1259/LT1260

Enable/Disable

The LT1259/LT1260 amplifiers have a unique high imped-

ance, zero supply current mode which is controlled by

independent EN pins. When disabled, an amplifier output

The input slew rate of the LT1259/LT1260 is approxi-

mately 270V/

µs and is set by internal currents and capaci-

tances. The output slew rate is set by the value of the

feedback resistors and internal capacitances. At a gain of

10 with at 1k feedback resistor and

±15V supplies, the

output slew rate is typically 1600V/

µs. Larger feedback

resistors will reduce the slew rate as will lower supply

voltages, similar to the way the bandwidth is reduced.

The graph of Maximum Undistorted Output vs Frequency

relates the slew rate limitations to sinusoidal input for

various gains.

looks like a 4.4pF capacitor in parallel with a 75k resistor,

excluding feedback resistor effects. These amplifiers are

designed to operate with open drain logic: the EN pins have

internal pullups and the amplifiers draw zero current when

these pins are high. To activate an amplifier, its EN pin is

pulled to ground (or at least 2V below the positive supply).

The enable pin current is approximately 60

µA when

activated. Input referred switching transients with no

input signal applied are only 35mV positive and 80mV

LT1259/LT1260 • AI04

The enable/disable times are very fast when driven from

standard 5V logic. The amplifier enables in about 100ns

(50% point to 50% point) while operating on

±5V sup-

plies. Likewise the disable time is approximately 40ns

(50% point to 50% point) or 75ns to 90% of the final

value. The output decay time is set by the output capaci-

tance and load resistor.

LT1259/LT1260 • AI01

LT1259/LT1260 • AI02

OUTPUT

EN

Output Switching Transient

LT1259/LT1260 • AI03

OUTPUT

EN

APPLICATIO S I FOR ATIO