13

LT1218/LT1219

Shutdown

The biasing of the LT1218/LT1219 is controlled by the

SHDN pin. When the SHDN pin is low, the part is shut

down. In the shutdown mode, the output looks like a 40pF

capacitor and the supply current is less than 30

µA. The

SHDN pin is referenced to the positive supply through an

internal bias circuit (see Figure 1). The SHDN pin current

with the pin low is typically 3

µA.

The switching time between the shutdown and active

states is about 20

µs, however, the total time to settle will

be greater by the slew time of the amplifier. For example,

if the DC voltage at the amplifier output is 0V in shutdown

and –2V in the active mode, an additional 20

µs is required.

Figures 4a and 4b show the switching waveforms for a

sinusoidal and a –2V DC input to the LT1218.

The SHDN pin can be driven directly from CMOS logic if the

logic and the LT1218/LT1219 are operated from the same

supplies. For higher supply operation, an interface is

required. An easy way to interface between supplies is to

use open-drain logic, an example is shown in Figure 5.

Because the SHDN pin is referenced to the positive supply,

the logic used should have a breakdown voltage greater

than the positive supply.

SHDN

LT1218/19 • F04a

Figure 4a

SHDN

LT1218/19 • F04a

Figure 4b

0V

0V

0V

0V

–15V

15V

LT1218/

LT1219

LT1218/19 • F05

SHDN

5V

SHDN

74C906

Figure 5. Shutdown Interface

Trim Pins

Trim pins are provided for compatibility with other single

op amps. Input offset voltage can be adjusted over a

±2.3mV range with a 10k potentiometer.

2

3

4

1

8

7

10k

OUT

LT1218/

LT1219

LT1218/19 • F06

Figure 6. Optional Offset Nulling

Improved Supply Rejection in the LT1219

The LT1219 is a variation of the LT1218 offering greater

supply rejection and lower high frequency output imped-

ance. The LT1219 requires a 0.1

µF load capacitance for