LTC3448_15 datasheet(13/20 Pages) LINER

13 / 20 page

LTC3448

3448f

APPLICATIO S I FOR ATIO

with COUT, causing a rapid drop in VOUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

the load rise time is limited to approximately (25 • CLOAD).

Thus, a 10

µF capacitor charging to 3.3V would require a

250

µs rise time, limiting the charging current to about

130mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3448. These items are also illustrated graphically in

Figures 7 and 8. Check the following in your layout:

1. The power traces, consisting of the GND trace, the SW

trace and the VIN trace should be kept short, direct and

wide.

2. Does the VFB pin connect directly to the feedback

resistors? The resistive divider R1/R2 must be con-

nected between the (+) plate of COUT and ground.

3. Does the (+) plate of CIN connect to VIN as closely as

possible? This capacitor provides the AC current to the

internal power MOSFETs.

4. Keep the switching node, SW, away from the sensitive

VFB node.

5. Keep the (–) plates of CIN and COUT as close as possible.

Design Example

As a design example, assume the LTC3448 is used in a

single lithium-ion battery-powered cellular phone

application. The VIN will be operating from a maximum of

4.2V down to about 2.7V. The load current requirement

is a maximum of 0.6A but most of the time it will be in

standby mode, requiring only 2mA. Efficiency at both low

Figure 7. LTC3448 Layout Design

Figure 8. LTC3448 Layout

VIN

RFB2

RFB1

CIN

VIN

LTC3448

FREQ

SYNC

3448 F07

RUN

VOUT

MODE

VFB

GND

COUT

CFF

VOUT

3448 F08

LTC3448 датащи(PDF) 13 Page - Linear Technology

LTC3448 датащи(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL