LT1183CS datasheet(10/24 Pages) LINER

10 / 24 page

LT1182/LT1183/LT1184/LT1184F

CCFL PGND (Pin 1): This pin is the emitter of an internal

NPN power switch. CCFL switch current flows through

this pin and permits internal, switch-current sensing. The

regulators provide a separate analog ground and power

ground(s) to isolate high current ground paths from low

current signal paths. Linear Technology recommends the

use of star-ground layout techniques.

ICCFL (Pin 2): This pin is the input to the CCFL lamp current

programming circuit. This pin internally regulates to 450mV

(LT1182/LT1183) or 465mV (LT1184/LT1184F). The pin

accepts a DC input current signal of 0

µA to 100µA full

scale. This input signal is converted to a 0

µA to 500µA

source current at the CCFL VC pin. By shunt regulating the

ICCFL pin, the input programming current can be set with

DAC, PWM or potentiometer control. As input program-

ming current increases, the regulated lamp current in-

creases. For a typical 6mA lamp, the range of input

programming current is about 0

µA to 50µA.

DIO (Pin 3): This pin is the common connection between

the cathode and anode of two internal diodes. The remain-

ing terminals of the two diodes connect to ground. In a

grounded lamp configuration, DIO connects to the low

voltage side of the lamp. Bidirectional lamp current flows

in the DIO pin and thus the diodes conduct alternately on

half cycles. Lamp current is controlled by monitoring one-

half of the average lamp current. The diode conducting on

negative half cycles has one-tenth of its current diverted to

the CCFL VC pin. This current nulls against the source

current provided by the lamp-current programmer circuit.

A single capacitor on the CCFL VC pin provides both stable

loop compensation and an averaging function to the half-

wave-rectified sinusoidal lamp current. Therefore, input

programming current relates to one-half of average lamp

current. This scheme reduces the number of loop com-

pensation components and permits faster loop transient

response in comparison to previously published circuits.

If a floating-lamp configuration is used, ground the DIO

pin.

CCFL VC (Pin 4): This pin is the output of the lamp current

programmer circuit and the input of the current compara-

tor for the CCFL regulator. Its uses include frequency

compensation, lamp-current averaging for grounded lamp

circuits, and current limiting. The voltage on the CCFL VC

pin determines the current trip level for switch turnoff.

During normal operation this pin sits at a voltage between

0.95V (zero switch current) and 2.0V (maximum switch

current) with respect to analog ground (AGND). This pin

has a high impedance output and permits external voltage

clamping to adjust current limit. A single capacitor to

ground provides stable loop compensation. This simpli-

fied loop compensation method permits the CCFL regula-

tor to exhibit single-pole transient response behavior and

virtually eliminates transformer output overshoot.

AGND (Pin 5): This pin is the low current analog ground.

It is the negative sense terminal for the internal 1.24V

reference and the ICCFL summing voltage in the LT1182/

LT1183/LT1184/LT1184F. It is also a sense terminal for

the LCD dual input error amplifier in the LT1182/LT1183.

Connect external feedback divider networks that terminate

to ground and frequency compensation components that

terminate to ground directly to this pin for best regulation

and performance.

SHUTDOWN (Pin 6): Pulling this pin low causes complete

regulator shutdown with quiescent current typically re-

duced to 35

µA. The nominal threshold voltage for this pin

is 0.85V. If the pin is not used, it can float high or be pulled

to a logic high level (maximum of 6V). Carefully evaluate

active operation when allowing the pin to float high.

Capacitive coupling into the pin from switching transients

could cause erratic operation.

CCFL VSW (Pin 16): This pin is the collector of the internal

NPN power switch for the CCFL regulator. The power

switch provides a minimum of 1.25A. Maximum switch

current is a function of duty cycle as internal slope com-

pensation ensures stability with duty cycles greater than

50%. Using a driver loop to automatically adapt base drive

current to the minimum required to keep the switch in a

quasi-saturation state yields fast switching times and high

efficiency operation. The ratio of switch current to driver

current is about 50:1.

PIN FUNCTIONS

LT1183CS датащи(PDF) 10 Page - Linear Technology

LT1183CS датащи(HTML) 10 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL