5

LT1168

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be imparied.

Note 2: If the input voltage exceeds the supplies, the input current should

be limited to less than 20mA.

Note 3: A heat sink may be required to keep the junction temperature

below absolute maximum.

Note 4: The LT1168AC/LT1168C are guaranteed functional over the

operating temperature range of – 40

°C and 85°C.

Note 5: The LT1168AC/LT1168C are guaranteed to meet specified

performance from 0

°C to 70°C. The LT1168AC/LT1168C are designed,

characterized and expected to meet specified performance from – 40

°C to

85

°C but are not tested or QA sampled at these temperatures. The

LT1168AI/LT1168I are guaranteed to meet specified performance from

–40

°C to 85°C.

Note 6: Typical parameters are defined as the 60% of the yield parameter

distribution.

Note 8: This parameter is measured in a high speed automatic tester that

does not measure the thermal effects with longer time constants. The

magnitude of these thermal effects are dependent on the package used,

heat sinking and air flow conditions.

Note 9: This parameter is not 100% tested.

Note 10: Hysteresis in offset voltage is created by package stress that

differs depending on whether the IC was previously at a higher or lower

temperature. Offset voltage hysteresis is always measured at 25

°C, but

the IC is cycled to 85

°C I-grade (or 70°C C-grade) or –40°C I-grade

(0

°C C-grade) before successive measurement. 60% of the parts will

pass the typical limit on the data sheet.

ELECTRICAL CHARACTERISTICS

LT1168AI

LT1168I

SYMBOL

PARAMETER

CONDITIONS (Note 6)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Total Input Referred Offset Voltage

Input Offset Voltage

q

20

75

25

100

µV

Input Offset Voltage Hysteresis

(Notes 7, 10)

q

3.0

3.0

µV

Output Offset Voltage

q

180

500

200

600

µV

Output Offset Voltage Hysteresis (Notes 7, 10)

q

30

30

µV

Input Offset Drift (RTI)

(Note 9)

q

0.05

0.3

0.06

0.4

µV/°C

Output Offset Drift

(Note 9)

q

0.8

5

1

6

µV/°C

Input Offset Current

q

110

550

120

700

pA

Input Offset Current Drift

q

0.3

0.3

pA/

°C

Input Bias Current

q

120

500

220

800

pA

Input Bias Current Drift

q

1.4

1.4

pA/

°C

Input Voltage Range

q

V

q

V

CMRR

Common Mode

1k Source Imbalance,

Rejection Ratio

G = 1

q

86

90

81

90

dB

G = 10

q

98

105

95

105

dB

G = 100

q

114

118

112

118

dB

G = 1000

q

116

133

112

133

dB

PSRR

Power Supply

Rejection Ratio

G = 1

q

100

112

95

112

dB

G = 10

q

120

125

115

125

dB

G = 100

q

125

132

120

132

dB

G = 1000

q

128

140

125

140

dB

Supply Current

q

420

650

420

650

µA

Output Voltage Swing

q

V

q

V

Output Current

q

15

22

15

22

mA

SR

Slew Rate

q

0.22

0.41

0.22

0.42

V/

µs

Voltage Range

(Note 9)

q

V