Peripheral migration

AN4617

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DocID027161 Rev 1

2.18

I2C interface

Both STM32F0 and STM32L0 series embed compatible I2C peripherals. Although the L0

features an enhanced version correcting some minor bugs of the older one used on F0, the

programming procedures and registers are the same. Note that STM32L07x devices feature

up to 3 instances of the I2C.

2.19

USART interface

The STM32L0 series embeds an enhanced USART compared with the F0 series, but the

devices are compatible from the user point of view, as the programming procedures and

registers remain the same.

Maximum speed is 6 MBits/s for STM32F0, 4 MBits/s only for STM32L0 devices. Number of

instances is product dependent.

The main difference is implementing low power UART baud rate generator on STM32F0.

Not all the applied instances support all the available features. Refer to reference manuals

to check the range and supported communication.

The STM32L0 series features low power asynchronous UART supporting clocking from LSE

(up to 9.6 KBd) and communication at stop mode. The features supported by this peripheral

are limited vs. standard USARTs.

2.20

TSC interface

Both STM32F0 and STM32L0 series embed the same TSC interface, the only difference is

the pinout concerning specific pins. While STM32F0 uses ports PA, PB, PD and PE, the

STM32L0 uses PA, PB and PC. Configuration control and registers are the same.

2.21

Debug module

User can expect differences in mapping of bits at peripheral freezing registers and debug

sleep mode supported in STM32L0 devices.

Table 17. SPI differences between STM32F0 and STM32L0 series

SPI feature

STM32F0

STM32L0

Max speed

18 MBits/s

16 MBits/s

Data size

Programmable 4-16 bits

Fixed 8 or 16-bit

Data buffers

32-bit Tx & Rx FIFOs (up to 4 data frames)

16-bit Tx & Rx buffers (single data frame)

Data packing

Data packing (8 & 16 & 32-bit access,

programmable FIFOs data threshold)

Not available

Instances

1-2x SPI (inc. 1-2x I2S)

2x SPI (inc. 1x I2S)